Intel® Server System Server System "Emerald Ridge ... - CTL

錯 誤 ! 尚 未 定 義 樣 式 。 EPSFunctional Specification3.14.1 Processor Status SensorsThe BMC provides an IPMI sensor of type processor for monitoring status information for eachprocessor slot. If an event state (sensor offset) has been asserted, it remains asserted until oneof the following happens:A Rearm Sensor Events command is executed for the processor status sensor.AC or DC power cycle, system reset, or system boot occurs.The BMC provides system status indication to the front panel LEDs for processor faultconditions shown in the table below. See Section 3.6.2.CPU Presence status is not saved across AC power cycles and so will not generate adeassertion after cycling AC power.Table 11. Processor Status Sensor ImplementationOffsetProcessor StatusDetected By0 Internal error (IERR) Not Supported1 Thermal trip BMC2 FRB1 / BIST failure Not Supported3 FRB2 / Hang in POST failure BIOS 14 FRB3 / Processor startup / initialization failure (CPU fails tostart)5 Configuration error (for DMI) BIOS 1Not Supported6 SM BIOS uncorrectable CPU-complex error Not Supported7 Processor presence detected BMC8 Processor disabled Not Supported9 Terminator presence detected Not SupportedNote: Fault is not reflected in the processor status sensor.3.14.1.1 Processor PresenceWhen the BMC detects an empty processor socket, it sets the disable bit in the processor statusfor that socket and clears the remaining status bits.Upon BMC initialization, the processor presence offset is initialized to the de-asserted state. TheBMC then checks to see if the processor is present, setting the offset accordingly. This state isupdated at each DC power-on and at system resets. If a processor is removed while the systemhas AC power, and the system is then powered-on (DC-on), the appropriate deassertion eventwill be logged (if enabled). The net effect is that there should be one event logged for processorpresence at BMC initialization for each installed processor, assuming the SDR is configured togenerate the event. No additional events for processor presence are expected unless thesensor is manually re-armed using an IPMI command.3.14.1.2 Thermtrip MonitoringWhen a thermtrip occurs it is detected by the IOH and the system hardware will attempt topower-down the system. The BMC latches the thermtrip signal to retain a history for eachprocessor. This history tracks whether the processor has had a thermtrip since the lastRevision 1.1Intel ® Confidential 25