IntelÃ‚Â® Server System Server System "Emerald Ridge ... - CTL

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錯誤 ! 尚未定義樣式。 EPSFunctional Specification3.4 <strong>System</strong> InitializationThe following items are initialized by both the BIOS and the BMC during system initialization.3.4.1 Processor TControl SettingProcessors used with this chipset implement a feature called Tcontrol, which provides aprocessor-specific value that can be used to adjust the fan control behavior to achieve optimumcooling and acoustics. The BMC reads these values directly from the CPU via PECI. The BMCuses these values as part of the fan speed control algorithm. See Section 3.16.4.2.3.4.2 Fault Resilient Booting (FRB)Fault resilient booting (FRB) is a set of BIOS and BMC algorithms and hardware support thatallow a multiprocessor system to boot even if the bootstrap processor (BSP) fails. Only FRB2 issupported, using watchdog timer commands.FRB2 refers to the FRB algorithm that detects system failures during the POST. The BIOS usesthe BMC watchdog timer to back up its operation during POST. The BIOS configures thewatchdog timer to indicate that the BIOS is using the timer for the FRB2 phase of the bootoperation.After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit andloads the watchdog timer with the new timeout interval.If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC (if soconfigured) logs a watchdog expiration event showing the FRB2 timeout in the event data bytes.The BMC then hard resets the system, assuming the BIOS selected reset as the watchdogtimeout action.The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scanand before displaying a request for a boot password. If the processor fails and causes an FRB2time-out, the BMC resets the system.The BIOS gets the watchdog expiration status from the BMC. If the status shows an expiredFRB2 timer, the BIOS enters the failure in the system event log (SEL). In the OEM bytes entryin the SEL, the last POST code generated during the previous boot attempt is written. FRB2failure is not reflected in the processor status sensor value.The FRB2 failure does not affect the front panel LEDs.3.4.2.1 Watchdog Timer Timeout Reason BitsTo implement FRB2, during POST the BIOS determines if a BMC watchdog timer timeoutoccurred on the previous boot attempt. If it finds a watchdog timeout did occur, it determineswhether that timeout was an FRB2 timeout, system management software (SMS) timeout, or anintentional, timed hard reset. The BMC provides the IPMI Get Watchdog Timer command tofacilitate determining the cause of the watchdog time out.The BMC maintains the timeout-reason bits across system resets and DC power cycles, but notacross AC power cycles.Revision 1.1Intel ® Confidential 13
錯誤 ! 尚未定義樣式。錯誤 ! 尚未定義樣式。 EPS3.4.3 BSP IdentificationThe BMC cannot indicate which processor is the BSP. Software that needs to identify the BSPshould use the multiprocessor specification tables. See the BIOS EPS.3.4.4 Boot Control SupportThe BMC supports the IPMI 2.0 boot control feature that allows the boot device and bootparameters to be managed remotely. Table 40 specifies the supported boot option parameters.The boot initiator mailbox is five 16-byte blocks.3.4.5 Post Code DisplayThe BMC, upon receiving standby power, initializes internal hardware to monitor port 80h(POST code) writes. Data written to port 80h is output to the system POST LEDs. Note thatalthough the port 80h data is read by a hardware FIFO, output to the LEDs is driven by firmware.This could lead to delays between the write and subsequent display on the LEDs. There is alsono flow control for port 80h writes, so a burst of data could result in the old POST codes beingdropped from the FIFO before being displayed on the LEDs.The BMC core firmware does not guarantee any specific rate at which the FIFO’s contents willbe displayed to the LEDs.The BMC deactivates POST LEDs after POST has completed.3.4.6 BMC Resident SMBIOS Data Storage (Managed Data Region)The BMC maintains a copy of a SMBIOS table header and all Type 04h, 16h, and 17h records.This SMBIOS data can be retrieved using OEM IPMI commands either in-band or out-of-band.Once retrieved, external applications may interpret this data by decoding the information asdescribed by the current SMBIOS Specification.Internally to the BMC, the SMBIOS data is stored in a multi-purpose Managed Data Region(MDR) that is maintained in BMC accessible RAM. Note that the MDR was originally defined bythe Compute Blade BMC Data Repository Specification.On all system boots following an AC cycle, the BIOS sends a copy of the relevant SMBIOS datato the BMC during POST. On all other system boots, the BIOS checks late in the POST processwhether the BMC already has SMBIOS data that matches the SMBIOS information which wouldbe sent by the BIOS. This determination is done by the BIOS querying the BMC to see if it hasSMBIOS data and, if it does, whether the length and checksum of the SMBIOS data matchesthe length and checksum of the information to be sent. If the BIOS determines that the BMCdata needs to be refreshed – it will send a fresh copy of the SMBIOS data to the BMC.Since the SMBIOS data is maintained by the BMC in RAM, it is not available following afirmware update, upon entering and exiting firmware transfer mode, or after any other time inwhich BMC restarts.Table 59 lists OEM IPMI command exposed to send and retrieve data. Due to IPMI commandlength limitations, multiple calls to the OEM IPMI interface will be required to obtain all of theembedded software information.14Intel ConfidentialRevision 1.1
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