Intel® Server System Server System "Emerald Ridge ... - CTL

Intel® Server System "Emerald Ridge” Integrated Baseboard Management Controller EPSIPMI Command InterfaceCodeD6hCommandSet HostCPU dataTable 57. Intel General Application Commands for Management EngineRequestNet Function = Intel General Application (0x2E2E), LUN = 00Request, Response DataByte 1:3 = Intel manufacturers ID – 0x000157,LS byte firstByte 4 – Domain Id[0:3] = Domain Id (Identifies the set ofprocessors supported by the domain. Currently,FW supports only one domain, Domain 0.)[4:7] = Reserved. Write as 0000b.Byte 5 – Host CPU data.[7] – Set to 1 for End of POST notification[6:5] – Reserved. Write as 00b1[1][4] – Set to 1 if Host CPU discovery data isprovided with that command. This informationshould be passed to Node Manager on eachplatform boot.[3:0] – Reserved. Write as 000b.Note: The Bytes 25:6 are ignored if Byte 5 bit[4] is set to 0.If Byte 5 bit [4] is set to 1 Bytes 24:6 shoulddescribe the actual Host CPU data of theplatform. Additionally, Bytes 24:6 should be setto 0 if the CPU discovery data is passed to NMdirectly by the BIOS.Per processor discovery data will be providedonly for the lowest number processor that isinstalled. In the multiprocessor environment, allother installed processors should match thenumber of performance states, and eachprocessor performance state must haveidentical performance and power-consumptionparameters.Byte 6 – Number of P-States supported by thecurrent platform CPU configuration:= 0 – If P-states are disabled by the user.= 1 – If the CPU does not support P-states orsome of the installed processors don’t matchthe lowest number processor powerconsumptionparameters.= 2..255 – The actual number of supportedP-States by the lowest number processor.Note: other processors should match thenumber of performance states of the lowestnumber processor.Byte 7 – Number of T-States supported by theDescriptionThis command is optional and may beunavailable on certain implementations.Note: This command is mandatory ifNode Manager is a part of the SPSFirmware and if BIOS does notimplement HECI-1 communication toME. This information should be passedto the Node Manager on each platformboot and after each CPU insert/removal.Revision 1.1Intel ® Confidential 117