User Manual High Performance AC Drive

Programming and Parameters 3-37NameNo. Description251 FB Opt0 Spd FdbkDisplays the speed feedback from the feedback option card port 0.252 FB Opt1 PositDisplays position feedback (accumulator) from port 1 of the feedback option card.253 FB Opt1 Spd FdbkDisplays speed feedback from port 1 of the feedback option card.Units:Default:Min/Max:Scale:Default:Min/Max:UnitsDefault:Min/Max:RPM0.0000-/+14000.0000Par 4 [Motor NP RPM] = 1.0pu00/2147483648RPM0.0-/+8.0 puRO RealRO 32-bitIntegerRO Real254 Opt0/1 RegisCnfgConfigures the registration latch for port 0 of the feedback option card.• Bits 3 [O0 RLTrgEdg0], 4 [O0 RLTrgEdg1], 19 [O1 RLTrgEdg0] and 20 [O1 RLTrgEdg1] select which trigger edges signal the position (see Par Table 254A: EdgeSelection Settings).• Bits 5 [O0 RL DirRev], 6 [O0 RL DirFwd], 21 [O1 RL DirRev] and 22 [O1 RL DirFwd] set the direction of position capture (see Par Table 254B: DirectionSettings).• Bits 8-11 configure a digital filter for the registration trigger signal. This filter can be used to reject spurious noise. The filter works by waiting a programmed timebefore deciding that the signal is valid. This waiting imposes a mandatory delay in the registration signal. The filter delay is programmable in increments of 100nanoseconds from 0 (or no delay) up to 700 nanoseconds.OptionsDefault 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Bits 3 & 4, 19 & 20, please refer to Table 254A: Edge Selection Settings below:ValuesReservedReservedReservedReservedReservedReservedReservedReservedReservedO1 RL DirFwdO1 RL DirRevO1 RLTrgEdg1O1 RLTrgEdg0ReservedReservedReservedReservedReservedReservedReservedRL Filt bit3RL Filt bit2RL Filt bit1RL Filt bit0ReservedO0 RL DirFwdO0 RL DirRevO0 RLTrgEdg1O0 RLTrgEdg0ReservedReservedReservedLinkableRead-WriteData Type0 = False1 = TrueTable 254A: Edge Selection SettingsBit 4/20 3/190 0 Capture on rising edge0 1 Capture on falling edge1 0 Capture on both edges1 1 Disable captureTable 254B: Direction SettingsBit 6/22 5/210 0 Disable capture0 1 Capture position during Reverse rotation1 0 Capture position during Forward rotation1 1 Capture position during either rotation255 Opt0/1 RegisCtrlConfigures the registration control on port 0 of the feedback option card.• Set bits 0 [O0 Arm Req] and 16 [01 Arm Req] to arm the registration logic for the next trigger event. The particular latch will be armed and ready to be strobedon the next occurrence of the trigger input.• Set bits 1 [O0 DisarmReq] and 17 [01 DisarmReq] to disarm the registration logic for next trigger event.After the registration is captured, bit 0 [O0 Arm Req] and bit 16 [O1 Arm Req] automatically resets back to 0 after found. Bit 1 [O0 DisarmReq and bit 17 [O1DisarmReq] are only needed to disarm a registration latch that has not been found yet. Setting bits 1 and 17 will clear the bits 0 and 6. Setting bits 0 and 6 sets bits0 [Opt0 Armed] and bit 16 [Opt1 Armed] and clears bits 1 [Opt0 Found] and bit 17 [Opt1 Found] of parameter 256 [Opt0/1 RegisStat].OptionsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedO1 DisarmReqO1 Arm ReqReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedO0 DisarmReqO0 Arm ReqDefault 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0256 Opt0/1 RegisStatIndicates the registration control status on port 0 of the feedback option card.• Bit 0 [Opt0 Armed] indicates the registration latch is armed.• Bit 1 [Opt0 Found] indicates the registration event has triggered the latch.• Rising edge of 'Arm request' will set the 'Armed' status bit.• Rising edge of 'Disarm request' will clear the 'Armed' status bit.OptionsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedOpt1 FoundOpt1 ArmedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedOpt0 FoundOpt0 ArmedDefault 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 = False1 = True0 = False1 = True