User Manual High Performance AC Drive

3-38 Programming and ParametersNo.NameDescription257 Opt 0 Regis LtchDisplays the registration data of the feedback option card port 0. The registration data is theposition reference counter value latched by the external strobes. The strobe signal used totrigger the latch is configurable by the Par 254 [Opt0/1 RegisCnfg].258 Opt 1 Regis LtchDisplays the registration data of the feedback option card port 0. The registration data is theposition reference counter value latched by the external strobes. The strobe signal used totrigger the latch is configurable by the Par 254 [Opt0/1 RegisCnfg].Default:Min/Max:Default:Min/Max:0-/+21474836480-/+2147483648RO 32-bitIntegerRO 32-bitInteger259 Stegmann0 CnfgConfigures the Stegmann Hi-Resolution Encoder Feedback Option.• Bit 5 [Direction] determines counting direction. If clear, direction is forward or up. If set, the direction is reverse or down.• Bits 10 [SmplRate bt0] -12 [SmplRate bt2] configure the Finite Impulse Response (FIR) Filter (see Par Table 259A: FIR Filter Settings). This setting reduces theeffect of noisy feedback on the system. Refer to the Speed/Position Feedback section of the PowerFlex® 700S with Phase II Control Reference Manual,publication PFLEX-RM003 for details.Notes: Bit 11 [SmplRate bt1] is set to 0 = False by default for firmware version 1.11 and is set to 1 = True by default for firmware version 2.03. This parameter waschanged to non-linkable for firmware version 3.01.ValuesLinkableRead-WriteData TypeOptionsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedSmplRate bt2SmplRate bt1SmplRate bt0ReservedReservedReservedSW ResetDirectionReservedReservedReservedReservedReservedDefault 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 = False1 = TrueTable 259A: FIR Filter SettingsBit 12 11 10 Taps0 0 0 10 0 1 20 1 0 40 1 1 81 0 0 161 0 1 321 1 0 641 1 1 127260 Stegmann0 StatusIndicates faults on the Stegmann Hi-Resolution Encoder Feedback Option.• Bit 8 [Open Wire] indicates an open wire fault.The feedback option card checks for a pre-determined constant value. If this value is not within tolerances, an open wire fault is declared. A quadrature checkalso is done. If an error occurs during the check, the ope wire check is aborted. If 3 quadrature errors occur in succession, the open wire check will completeand the constant value checked again. If this value is not within tolerances, the fault is declared.• Bit 9 [PowerSup Er] indicates the failure of the power supply.• Bit 10 [PwrUpDiag Er] indicates the option board failed its power-up diagnostic test.The pattern on the FPGA must be identical to the pattern written from the DSP, or the board status test will fail.• Bit 11 [MsgChksum Er] indicates a message checksum fault.The check sum associated with the Heidenhain encoder must be correct and acknowledged by the feedback option card.• Bit 12 [Time Out Err] indicates a RS-485 time-out fault.This check requires information to be sent from the encoder to the feedback option card within a specified time. Typical times are about 10 clock cycles beforeand error is detected. This check is done only at power-up.OptionsReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedReservedTime Out ErrMsgChksum ErPwrUpDiag ErPowerSup ErOpen WireReservedReservedReservedReservedReservedReservedReservedReservedDefault 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 = False1 = True