Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

C8051F120/1/2/3
C8051F124/5/6/7
Preliminary
Figure 8.7. DAC1CN: DAC1 Control Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
DAC1EN - - DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address: 0xD4
SFR Page: 1
Bit7:
Bits6-5:
Bits4-3:
Bits2-0:
DAC1EN: DAC1 Enable Bit.
0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode.
1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational.
UNUSED. Read = 00b; Write = don’t care.
DAC1MD1-0: DAC1 Mode Bits:
00: DAC output updates occur on a write to DAC1H.
01: DAC output updates occur on Timer 3 overflow.
10: DAC output updates occur on Timer 4 overflow.
11: DAC output updates occur on Timer 2 overflow.
DAC1DF2: DAC1 Data Format Bits:
000: The most significant nibble of the DAC1 Data Word is in DAC1H[3:0], while the least
significant byte is in DAC1L.
DAC1H
DAC1L
MSB
LSB
001: The most significant 5-bits of the DAC1 Data Word is in DAC1H[4:0], while the least
significant 7-bits are in DAC1L[7:1].
DAC1H
DAC1L
MSB
LSB
010: The most significant 6-bits of the DAC1 Data Word is in DAC1H[5:0], while the least
significant 6-bits are in DAC1L[7:2].
DAC1H
DAC1L
MSB
LSB
011: The most significant 7-bits of the DAC1 Data Word is in DAC1H[6:0], while the least
significant 5-bits are in DAC1L[7:3].
DAC1H
DAC1L
MSB
LSB
MSB
1xx:
The most significant 8-bits of the DAC1 Data Word is in DAC1H[7:0], while the least
significant 4-bits are in DAC1L[7:4].
DAC1H
DAC1L
LSB
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DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.