Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 22.1. Enhanced Baud Rate Generation The UART1 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 22.2), which is not user-accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state. Figure 22.2. UART1 Baud Rate Logic Timer 1 UART1 TL1 Overflow 2 TX Clock TH1 Start Detected RX Timer Overflow 2 RX Clock Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “23.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload” on page 277). The Timer 1 reload value should be set so that overflows will occur at two times the desired baud rate. Note that Timer 1 may be clocked by one of five sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external oscillator clock / 8. For any given Timer 1 clock source, the UART1 baud rate is determined by Equation 22.1. Equation 22.1. UART1 Baud Rate UARTBaudRate = T1 CLK 1 ------------------------------ × -- ( 256 – T1H) 2 Where T1 CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in Section “23.1. Timer 0 and Timer 1” on page 275.Aquickreference for typical baud rates and system clock frequencies is given in Table 22.1 through Table 22.5. Note that the internal oscillator or PLL may still generate the system clock when the external oscillator is driving Timer 1 (see Section “23.1. Timer 0 and Timer 1” on page 275 for more details). Page 266 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 22.2. Operational Modes UART1 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S1MODE bit (SCON1.7). Typical UART connection options are shown below. Figure 22.3. UART Interconnect Diagram RS-232 RS-232 LEVEL XLTR TX RX C8051Fxxx OR MCU TX RX TX C8051Fxxx RX 22.2.1. 8-Bit UART 8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX1 pin and received at the RX1 pin. On receive, the eight data bits are stored in SBUF1 and the stop bit goes into RB81 (SCON1.2). Data transmission begins when software writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met: RI1 must be logic 0, and if MCE1 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF1 receive register and the following overrun data bits are lost. Iftheseconditionsaremet,theeightbitsofdataisstoredinSBUF1,thestopbitisstoredinRB81andtheRI1flagis set. If these conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set. An interrupt will occur if enabled when either TI1 or RI1 is set. Figure 22.4. 8-Bit UART Timing Diagram MARK SPACE START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT BIT TIMES BIT SAMPLING © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 267
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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