Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 4.4. TQFP-64 Package Drawing D D1 MIN (mm) NOM (mm) MAX (mm) A - - 1.20 A1 0.05 - 0.15 E1 E A2 0.95 - 1.05 b 0.17 0.22 0.27 64 D - 12.00 - PIN 1 DESIGNATOR A2 1 e D1 e E - - - 10.00 0.50 12.00 - - - b A1 A E1 - 10.00 - Page 46 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 5. ADC0 (12-BIT ADC, C8051F120/1/4/5 ONLY) The ADC0 subsystem for the C8051F120/1/4/5 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see block diagram in Figure 5.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Registers shown in Figure 5.1. The voltage reference used by ADC0 is selected as described in Section “9. VOLTAGE REFERENCE (C8051F120/2/4/6)” on page 105 for C8051F120/2/4/6 devices, or Section “10. VOLTAGE REF- ERENCE (C8051F121/3/5/7)” on page 107 for C8051F121/3/5/7 devices. The ADC0 subsystem (ADC0, trackand-hold and PGA0) is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0. Figure 5.1. 12-Bit ADC0 Functional Block Diagram ADC0GTH ADC0GTL ADC0LTH ADC0LTL 24 Comb. Logic AD0WINT AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 + - + - + - + - 9-to-1 AMUX (SE or DIFF) X + - AD0EN AV+ AGND AV+ 12-Bit SAR ADC SYSCLK REF 12 ADC0L ADC0H 12 TEMP SENSOR AGND AIN67IC AIN45IC AIN23IC AIN01IC AMX0CF AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 AMX0SL AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AMP0GN2 AMP0GN1 AMP0GN0 ADC0CF AD0CM AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 AD0WINT AD0LJST ADC0CN Start Conversion 00 01 10 11 AD0CM AD0BUSY (W) Timer 3 Overflow CNVSTR0 Timer 2 Overflow 5.1. Analog Multiplexer and PGA Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected to an on-chip temperature sensor (temperature transfer function is shown in Figure 5.2). AMUX input pairs can be programmed to operate in either differential or single-ended mode. This allows the user to select the best measurement technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 5.6), and the Configuration register AMX0CF (Figure 5.5). The table in Figure 5.6 shows AMUX functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 5.7). The PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 47
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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