Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON (see Figure 23.6). Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal /INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /INT0 (see Section “12.7.5. Interrupt Register Descriptions” on page 147), facilitating pulse width measurements. TR0 GATE0 /INT0 Counter/Timer 0 X X Disabled 1 0 X Enabled 1 1 0 Disabled 1 1 1 Enabled X = Don't Care Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled. TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is used with Timer 1. Figure 23.1. T0 Mode 0 Block Diagram CKCON T T S S 1 0 C C M M A A 1 0 G A T E 1 C / T 1 TMOD T T G C 1 1 A / M M T T 1 0 0 E 0 T 0 M 1 T 0 M 0 Pre-scaled Clock 0 0 SYSCLK 1 1 T0 Crossbar GATE0 TR0 TCLK TL0 (5 bits) TH0 (8 bits) TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt /INT0 23.1.2. Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. Page 276 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 23.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is low. Figure 23.2. T0 Mode 2 Block Diagram CKCON T T S S 1 0 C C M M A A 1 0 G A T E 1 C / T 1 TMOD T T G 1 1 A T M 1 M 0 E 0 C / T 0 T 0 M 1 T 0 M 0 Pre-scaled Clock 0 0 SYSCLK 1 1 T0 Crossbar GATE0 TR0 TCLK TL0 (8 bits) TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Interrupt TH0 (8 bits) Reload /INT0 © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 277
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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