Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Figure 17.12. Multiplexed 8-bit MOVX with Bank Select Timing Muxed 8-bit WRITE with Bank Select ADDR[15:8] P2/P6 EMIF ADDRESS (8 MSBs) from EMI0CN P2/P6 AD[7:0] P3/P7 EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF WRITE DATA P3/P7 T ALEH T ALEL ALE P0.5/P4.5 P0.5/P4.5 T WDS T WDH T ACS T ACW T ACH /WR P0.7/P4.7 P0.7/P4.7 /RD P0.6/P4.6 P0.6/P4.6 Muxed 8-bit READ with Bank Select ADDR[15:8] P2/P6 EMIF ADDRESS (8 MSBs) from EMI0CN P2/P6 AD[7:0] P3/P7 EMIF ADDRESS (8 LSBs) from R0 or R1 EMIF READ DATA P3/P7 T T ALEH ALEL T TRDH RDS ALE P0.5/P4.5 P0.5/P4.5 T ACS T ACW T ACH /RD P0.6/P4.6 P0.6/P4.6 /WR P0.7/P4.7 P0.7/P4.7 Page 200 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Table 17.1. AC Parameters for External Memory Interface PARAMETER DESCRIPTIONMINMAX UNITS T SYSCLK System Clock Period (C8051F120/1/2/3) 10 ns T SYSCLK System Clock Period (C8051F124/5/6/7) 20 ns T ACS Address / Control Setup Time 0 3*T SYSCLK ns T ACW Address / Control Pulse Width 1*T SYSCLK 16*T SYSCLK ns T ACH Address / Control Hold Time 0 3*T SYSCLK ns T ALEH Address Latch Enable High Time 1*T SYSCLK 4*T SYSCLK ns T ALEL Address Latch Enable Low Time 1*T SYSCLK 4*T SYSCLK ns T WDS WriteDataSetupTime 1*T SYSCLK 19*T SYSCLK ns T WDH WriteDataHoldTime 0 3*T SYSCLK ns T RDS Read Data Setup Time 20 ns T RDH Read Data Hold Time 0 ns © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 201
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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