Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 24.15. PCA0CPLn: PCA0 Capture Module Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: PCA0CPL0: 0xFB, PCA0CPL1: 0xFD, PCA0CPL2: 0xE9, PCA0CPL3: 0xEB, PCA0CPL4: 0xED, PCA0CPL5: 0xE1 SFR Page: PCA0CPL0: page 0, PCA0CPL1: page 0, PCA0CPL2: page 0, PCA0CPL3: page 0, PCA0CPL4: page 0, PCA0CPL5: page 0 \ Bits7-0: PCA0CPLn: PCA0 Capture Module Low Byte. The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n. Figure 24.16. PCA0CPHn: PCA0 Capture Module High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: PCA0CPH0: 0xFC, PCA0CPH1: 0xFD, PCA0CPH2: 0xEA, PCA0CPH3: 0xEC, PCA0CPH4: 0xEE, PCA0CPH5: 0xE2 SFR Page: PCA0CPH0: page 0, PCA0CPH1: page 0, PCA0CPH2: page 0, PCA0CPH3: page 0, PCA0CPH4: page 0, PCA0CPH5: page 0 Bits7-0: PCA0CPHn: PCA0 Capture Module High Byte. The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n. Page 304 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 25. JTAG (IEEE 1149.1) Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification. The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO. Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 25.1 can be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with Flash read/write operations on the MCU. Figure 25.1. IR: JTAG Instruction Register Bit15 Bit0 Reset Value 0x0000 IR Value Instruction Description 0x0000 EXTEST Selects the Boundary Data Register for control and observability of all device pins 0x0002 SAMPLE/ Selects the Boundary Data Register for observability and presetting the scan-path PRELOAD latches 0x0004 IDCODE Selects device ID Register 0xFFFF BYPASS Selects Bypass Data Register 0x0082 Flash Control Selects FLASHCON Register to control how the interface logic responds to reads and writes to the FLASHDAT Register 0x0083 Flash Data Selects FLASHDAT Register for reads and writes to the Flash memory 0x0084 Flash Address Selects FLASHADR Register which holds the address of all Flash read, write, and erase operations 0x0085 Flash Scale Selects FLASHSCL Register which controls the Flash one-shot timer and readalways enable © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 305
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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