Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 13.7.2. Disable WDT Writing 0xDE followed by 0xAD to the WDTCN register disables the WDT. The following code segment illustrates disabling the WDT: CLR EA ; disable all interrupts MOV WDTCN,#0DEh ; disable software watchdog timer MOV WDTCN,#0ADh SETB EA ; re-enable interrupts The writes of 0xDE and 0xAD must occur within 4 clock cycles of each other, or the disable operation is ignored. Interrupts should be disabled during this procedure to avoid delay between the two writes. 13.7.3. Disable WDT Lockout Writing 0xFF to WDTCN locks out the disable feature. Once locked out, the disable operation is ignored until the next system reset. Writing 0xFF does not enable or reset the watchdog timer. Applications always intending to use the watchdog should write 0xFF to WDTCN in the initialization code. 13.7.4. Setting WDT Interval WDTCN.[2:0] control the watchdog timeout interval. The interval is given by the following equation: 4 3 + WDTCN[ 2– 0] × T sysclk ;whereT sysclk is the system clock period. For a 3 MHz system clock, this provides an interval range of 0.021 ms to 349.5 ms. WDTCN.7 must be logic 0 when setting this interval. Reading WDTCN returns the programmed interval. WDTCN.[2:0] reads 111b after a system reset. Figure 13.3. WDTCN: Watchdog Timer Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value xxxxx111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xFF SFR Page: All Pages Bits7-0: Bit4: Bits2-0: WDT Control Writing 0xA5 both enables and reloads the WDT. Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT. Writing 0xFF locks out the disable feature. Watchdog Status Bit (when Read) Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. Page 158 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 13.4. RSTSRC: Reset Source Register R R/W R/W R/W R R/W R R/W Reset Value - CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF PORSF PINRSF 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xEF SFR Page: 0 Bit7: Bit6: Bit5: Bit4: Bit3: Bit2: Bit1: Bit0: Reserved. CNVRSEF: Convert Start 0 Reset Source Enable and Flag Write: 0: CNVSTR0 is not a reset source. 1: CNVSTR0 is a reset source (active low). Read: 0:SourceofpriorresetwasnotCNVSTR0. 1: Source of prior reset was CNVSTR0. C0RSEF: Comparator0 Reset Enable and Flag. Write: 0: Comparator0 is not a reset source. 1: Comparator0 is a reset source (active low). Read: 0: Source of last reset was not Comparator0. 1: Source of last reset was Comparator0. SWRSF: Software Reset Force and Flag. Write: 0: No effect. 1: Forces an internal reset. /RST pin is not effected. Read: 0: Source of last reset was not a write to the SWRSF bit. 1: Source of last reset was a write to the SWRSF bit. WDTRSF: Watchdog Timer Reset Flag. 0: Source of last reset was not WDT timeout. 1: Source of last reset was WDT timeout. MCDRSF: Missing Clock Detector Flag. Write: 0: Missing Clock Detector disabled. 1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is detected. Read: 0: Source of last reset was not a Missing Clock Detector timeout. 1: Source of last reset was a Missing Clock Detector timeout. PORSF: Power-On Reset Flag. This bit is set anytime a power-on reset occurs. This may be due to a true power-on reset or a VDD monitor reset. In either case, data memory should be considered indeterminate following the reset. This reset is enabled/disabled using the external VDD monitor enable pin. 0: Source of last reset was not a power-on or VDD monitor reset. 1: Source of last reset was a power-on or VDD monitor reset. Note: When this flag is set, all other reset flags indeterminate. PINRSF: HW Pin Reset Flag. Write: 0: No effect. 1: Forces a Power-On Reset. /RST is driven low. Read: 0:Sourceofpriorresetwasnot/RSTpin. 1: Source of prior reset was /RST pin. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 159
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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