Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 1.2. C8051F121/125 Block Diagram VDD VDD VDD DGND DGND DGND AV+ AGND TCK TMS TDI TDO /RST MONEN XTAL1 XTAL2 VREF DAC1 DAC0 VREFA AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 CP0+ CP0- CP1+ CP1- Digital Power Analog Power JTAG Logic VDD Monitor A M U X CP0 VREF DAC1 (12-Bit) DAC0 (12-Bit) TEMP SENSOR Boundary Scan Debug HW WDT External Oscillator Circuit PLL Circuitry Calibrated Internal Oscillator CP1 Prog Gain Reset System Clock ADC 100ksps (12-Bit) 8 0 5 1 C o r e SFR Bus 256 byte RAM 8kbyte XRAM External Data Memory Bus 128kbyte FLASH 64x4 byte cache Port I/O Config. UART0 UART1 SMBus SPI Bus PCA Timers 0, 1, 2, 4 Timer 3/ RTC P0, P1, P2, P3 Latches Crossbar Config. Bus Control Address Bus Data Bus C T L A d d r D a t a C R O S S B A R ADC 500ksps (8-Bit) P4 Latch P5 Latch P6 Latch P7 Latch Prog Gain AV+ VREFA P0 Drv P1 Drv P2 Drv P3 Drv A M U X 8:1 P4 DRV P5 DRV P6 DRV P7 DRV P0.0 P0.7 P1.0/AIN2.0 P1.7/AIN2.7 P2.0 P2.7 P3.0 P3.7 Page 22 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 1.3. C8051F122/126 Block Diagram VDD VDD VDD DGND DGND DGND AV+ AV+ AGND AGND TCK TMS TDI TDO /RST MONEN XTAL1 XTAL2 VREF VREFD DAC1 DAC0 VREF0 AIN0.0 AIN0.1 AIN0.2 AIN0.3 AIN0.4 AIN0.5 AIN0.6 AIN0.7 CP0+ CP0- CP1+ CP1- Digital Power Analog Power JTAG Logic VDD Monitor A M U X CP0 VREF DAC1 (12-Bit) DAC0 (12-Bit) TEMP SENSOR Boundary Scan Debug HW WDT External Oscillator Circuit PLL Circuitry Calibrated Internal Oscillator CP1 Prog Gain Reset System Clock ADC 100ksps (10-Bit) 8 0 5 1 C o r e SFR Bus 256 byte RAM 8kbyte XRAM External Data Memory Bus 128kbyte FLASH 64x4 byte cache Port I/O Config. UART0 UART1 SMBus SPI Bus PCA Timers 0, 1, 2, 4 Timer 3/ RTC P0, P1, P2, P3 Latches Crossbar Config. Bus Control Address Bus Data Bus ADC 500ksps (8-Bit) C T L A d d r D a t a C R O S S B A R Prog Gain P4 Latch P5 Latch P6 Latch P7 Latch P0 Drv P1 Drv P2 Drv P3 Drv A M U X 8:1 P4 DRV P5 DRV P6 DRV P7 DRV P0.0 P0.7 P1.0/AIN2.0 P1.7/AIN2.7 P2.0 P2.7 P3.0 P3.7 VREF2 P4.0 P4.4 P4.5/ALE P4.6/RD P4.7/WR P5.0/A8 P5.7/A15 P6.0/A0 P6.7/A7 P7.0/D0 P7.7/D7 © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 23
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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