Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

Preliminary
C8051F120/1/2/3
C8051F124/5/6/7
12.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate
memory spaces: program memory and data memory. Program and data memory share the same address space but
are accessed via different instruction types. There are 256 bytes of internal data memory and 128k bytes of internal
program memory address space implemented within the CIP-51. The CIP-51 memory organization is shown in
Figure 12.2.
Figure 12.2. Memory Map
0x200FF
0x20000
0x1FFFF
0x1FC00
0x1FBFF
0x00000
PROGRAM/DATA MEMORY
(FLASH)
Scrachpad Memory
(DATA only)
RESERVED
FLASH
(In-System
Programmable in 1024
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Registers
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
0
1
2
3
Up To
256 SFR Pages
Off-chipXRAM space
0x2000
0x1FFF
0x0000
XRAM - 8192 Bytes
(accessable using MOVX
instruction)
12.2.1. Program Memory
The CIP-51 has a 128k byte program memory space. The MCU implements 131072 bytes of this program memory
space as in-system re-programmable FLASH memory in four 32k byte code banks. A common code bank (Bank 0)
of 32k bytes is always accessible from addresses 0x0000 to 0x7FFF. The three upper code banks (Bank 1, Bank 2,
and Bank 3) are each mapped to addresses 0x8000 to 0xFFFF, depending on the selection of bits in the PSBANK register,
as described in Figure 12.3. The IFBANK bits select which of the upper banks are used for code execution,
while the COBANK bits select the bank to be used for direct writes and reads of the FLASH memory. Note: 1024
bytes of the memory in Bank 3 (0x1FC00 to 0x1FFFF) are reserved and are not available for user program or data
storage.
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting
the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism
for the CIP-51 to update program code and use the program memory space for non-volatile data storage. Refer to Section
“15. FLASH MEMORY” on page 173 for further details.
© 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 123