Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 23.2.2. Capture Mode In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX input pin (Timer 3 shares the T2EX pin with Timer 2) causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers (RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6) will be set to ‘1’ and an interrupt will occur if the interrupt is enabled. See Section “12.7. Interrupt Handler” on page 144 for further information concerning the configuration of interrupt sources. As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be configured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to 0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will occur if enabled. Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn (TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4 respective External Enable EXENn (TnCON.3) must also be set to logic 1 to enable captures. If EXENn is cleared, transitions on TnEX will be ignored. Figure 23.11. T2, 3, and 4 Capture Mode Block Diagram TMRnCF T T T T D n n O n C M M G O E 1 0 n E N SYSCLK 12 2 0xFF 0xFF Toggle Logic 0 1 Tn (Port Pin) External Clock Tn TnEX 8 Crossbar EXENn Crossbar TRn 0 1 Capture TCLK TMRnL RCAPnL TMRnH RCAPnH OVF TnCON CP/RLn C/Tn TRn EXENn EXFn TFn Interrupt Page 284 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 23.2.3. Auto-Reload Mode In Auto-Reload Mode, the counter/timer can be configured to count up or down and cause an interrupt/flag to occur upon an overflow/underflow event. When counting up, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled) upon overflow/underflow, and the values in the Reload/Capture Registers (RCAPnH and RCAPnL) are loaded into the timer and the timer is restarted. When the Timer External Enable Bit (EXENn) bit is set to ‘1’ and the Decrement Enable Bit (DCEN) is ‘0’, a ‘0’-to-‘1’ transition on the TnEX pin will cause a timer reload. Note that timer overflows will also cause auto-reloads. When DCEN is set to ‘1’, the state of the TnEX pin controls whether the counter/timer counts up (increments) or down (decrements), and will not cause an auto-reload or interrupt event (Timer 3 shares the T2EX pin with Timer 2). See Section 23.2.1 for information concerning configuration of a timer to count down. When counting down, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled) when the value in the TMRnH and TMRnL registers matches the 16-bit value in the Reload/Capture Registers (RCAPnH and RCAPnL). This is considered an underflow event, and will cause the timer to load the value 0xFFFF. The timer is automatically restarted when an underflow occurs. Counter/Timer with Auto-Reload mode is selected by clearing the CP/RLn bit. Setting TRn to logic 1 enables and starts the timer. In Auto-Reload Mode, the External Flag (EXFn) toggles upon every overflow or underflow and does not cause an interrupt. The EXFn flag can be used as the most significant bit (MSB) of a 17-bit counter. . Figure 23.12. T2, 3, and 4 Auto-reload Mode Block Diagram TMRnCF T T T T D n n O n C M M G O E 1 0 n E N SYSCLK 12 2 0xFF 0xFF Toggle Logic 0 1 Tn (Port Pin) External Clock 8 Tn Crossbar TRn EXENn TnEX Crossbar 0 1 TCLK Reload TMRnL RCAPnL TMRnH RCAPnH OVF TnCON CP/RLn C/Tn TRn EXENn EXFn TFn Interrupt SMBus (Timer 4 Only) 23.2.4. Toggle Output Mode (Timer 2 and Timer 4 Only) Timers 2 and 4 have the capability to toggle the state of their respective output port pins (T2 or T4) to produce a 50% duty cycle waveform output. The port pin state will change upon the overflow or underflow of the respective timer (depending on whether the timer is counting up or down). The toggle frequency is determined by the clock source of © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 285
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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