Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

More documents

Recommendations

Info

C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 1.1.3. Additional Features The C8051F12x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be output on the /RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the user in software; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU initialization. The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the 24.5 MHz internal oscillator as needed. Additionally, an on-chip PLL is provided to achieve higher system clock speeds for increased throughput. Figure 1.5. On-Board Clock and Reset VDD (Port I/O) CP0+ CP0- Crossbar CNVSTR (CNVSTR reset enable) Comparator0 + - (CP0 reset enable) Supply Monitor + - Supply Reset Timeout (wired-OR) /RST Internal Clock Generator Missing Clock Detector (oneshot) EN MCD Enable WDT Enable WDT EN PRE WDT Strobe Reset Funnel XTAL1 XTAL2 PLL Circuitry OSC System Clock Clock Select CIP-51 Microcontroller Core Software Reset System Reset Extended Interrupt Handler Page 26 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The CIP-51 in the C8051F12x MCUs additionally has an on-chip 8k byte RAM block and an external memory interface (EMIF) for accessing off-chip data memory. The on-chip 8k byte block can be addressed over the entire 64k external data memory address range (overlapping 8k boundaries). External data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 8k directed to on-chip, above 8k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. The MCU’s program memory consists of 128k bytes of banked FLASH memory. This memory may be reprogrammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage. The 1024 bytes from addresses 0x1FC00 to 0x1FFFF are reserved. There are also two 128 byte sectors at addresses 0x20000 to 0x200FF, which may be used by software. See Figure 1.6 for the MCU system memory map. Figure 1.6. On-Chip Memory Map 0x200FF 0x20000 0x1FFFF 0x1FC00 0x1FBFF 0x00000 PROGRAM/DATA MEMORY (FLASH) Scrachpad Memory (DATA only) RESERVED FLASH (In-System Programmable in 1024 Byte Sectors) 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 0xFFFF DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers Special Function Registers (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) EXTERNAL DATA ADDRESS SPACE 0 1 2 3 Up To 256 SFR Pages Off-chipXRAM space 0x2000 0x1FFF 0x0000 XRAM - 8192 Bytes (accessable using MOVX instruction) © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 27
Page 1 and 2: Preliminary C8051F120/1/2/3 C8051F1
Page 25: Preliminary C8051F120/1/2/3 C8051F1
Page 43 and 44: © 2002 Cygnal Integrated Products,
Page 45 and 46: © 2002 Cygnal Integrated Products,
Page 77 and 78:
Preliminary C8051F120/1/2/3 C8051F1
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
Page 213 and 214:
Page 215 and 216:
Page 217 and 218:
Page 219 and 220:
Page 221 and 222:
Page 223 and 224:
Page 225 and 226:
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
Page 255 and 256:
Page 257 and 258:
Page 259 and 260:
Page 261 and 262:
Page 263 and 264:
Page 265 and 266:
Page 267 and 268:
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
show all

Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?