Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Table 11.1. Comparator Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS Response Time: CPn+ - CPn- = 100 mV 100 ns Mode 0, Vcm † =1.5V CPn+ - CPn- = -100 mV 250 ns Response Time: CPn+ - CPn- = 100 mV 175 ns Mode 1, Vcm † =1.5V CPn+ - CPn- = -100 mV 500 ns Response Time: CPn+ - CPn- = 100 mV 320 ns Mode 2, Vcm † =1.5V CPn+ - CPn- = -100 mV 1100 ns Response Time: CPn+ - CPn- = 100 mV 1050 ns Mode 3, Vcm † =1.5V CPn+ - CPn- = -100 mV 5200 ns Common-Mode Rejection Ratio 1.5 4 mV/V Positive Hysteresis 1 CPnHYP1-0 = 00 0 1 mV Positive Hysteresis 2 CPnHYP1-0 = 01 2 4.5 7 mV Positive Hysteresis 3 CPnHYP1-0 = 10 4 9 13 mV Positive Hysteresis 4 CPnHYP1-0 = 11 10 17 25 mV Negative Hysteresis 1 CPnHYN1-0 = 00 0 1 mV Negative Hysteresis 2 CPnHYN1-0 = 01 2 4.5 7 mV Negative Hysteresis 3 CPnHYN1-0 = 10 4 9 13 mV Negative Hysteresis 4 CPnHYN1-0 = 11 10 17 25 mV Inverting or Non-Inverting Input Voltage Range -0.25 (AV+) +0.25 Input Capacitance 7 pF Input Bias Current -5 0.001 +5 nA Input Offset Voltage -10 +10 mV POWER SUPPLY Power-up Time CPnEN from 0 to 1 20 µs Power Supply Rejection 0.1 1 mV/V Supply Current at DC (each comparator) Mode 0 7.6 µA Mode 1 3.2 µA Mode 2 1.3 µA Mode 3 0.4 µA V † V CM is the common-mode voltage on CPn+ and CPn-. Page 116 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 12. CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51 instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are five 16-bit counter/timers (see description in Section 23), two full-duplex UARTs (see description in Section 21 and Section 22), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space (see Section 12.2.6), and 8/4 byte-wide I/O Ports (see description in Section 18). The CIP-51 also includes on-chip debug hardware (see description in Section 25), and interfaces directly with the MCU’s analog and digital subsystems providing a complete data acquisition or controlsystem solution in a single integrated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 12.1 for a block diagram). The CIP-51 includes the following features: - Fully Compatible with MCS-51 Instruction Set - 100 or 50 MIPS Peak Using the On-Chip PLL - 256 Bytes of Internal RAM - 8/4 Byte-Wide I/O Ports - Extended Interrupt Handler - Reset Input - Power Management Modes - On-chip Debug Logic - Program and Data Memory Security Figure 12.1. CIP-51 Block Diagram DATA BUS B REGISTER DATA BUS PSW TMP1 ALU TMP2 D8 D8 D8 ACCUMULATOR D8 D8 SRAM ADDRESS REGISTER SRAM (256 X 8) D8 D8 D8 D8 STACK POINTER DATA BUS BUFFER DATA POINTER D8 D8 D8 SFR BUS INTERFACE SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA PC INCREMENTER RESET CLOCK STOP IDLE PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL LOGIC POWER CONTROL REGISTER PIPELINE D8 DATA BUS D8 A16 D8 D8 MEMORY INTERFACE INTERRUPT INTERFACE MEM_ADDRESS MEM_CONTROL MEM_WRITE_DATA MEM_READ_DATA SYSTEM_IRQs EMULATION_IRQ © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 117
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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