Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 16.4. CCH0CN: Cache Control Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CHWREN CHRDEN CHPFEN CHFLSH CHRETICHISR CHMOVC CHBLKW 11100110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA1 SFR Page: F Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: CHWREN: Cache Write Enable. This bit enables the processor to write to the cache memory. 0: Cache contents are not allowed to change, except during FLASH writes/erasures or cache locks. 1: Writes to cache memory are allowed. CHRDEN: Cache Read Enable. This bit enables the processor to read instructions from the cache memory. 0: All instruction data comes from FLASH memory or the prefetch engine. 1: Instruction data is obtained from cache (when available). CHPFEN: Cache Prefetch Enable. This bit enables the prefetch engine. 0: Prefetch engine is disabled. 1: Prefetch engine is enabled. CHFLSH: Cache Flush. When written to a ‘1’, this bit clears the cache contents. This bit always reads ‘0’. CHRETI: Cache RETI Destination Enable. This bit enables the destination of a RETIaddress to be cached. 0: Destinations of RETIinstructions will not be cached. 1: RETIdestinations will be cached. CHISR: Cache ISR Enable. This bit allows instructions which are part of an Interrupt Service Rountine (ISR) to be cached. 0: Instructions in ISRs will not be loaded into cache memory. 1: Instructions in ISRs can be cached. CHMOVC: Cache MOVC Enable. This bit allows data requested by a MOVC instruction to be loaded into the cache memory. 0: Data requested by MOVC instructions will not be cached. 1: Data requested by MOVC instructions will be loaded into cache memory. CHBLKW: Block Write Enable. This bit allows block writes to FLASH memory from software. 0: Each byte of a software FLASH write is written individually. 1: FLASH bytes are written in groups of four (for code space writes) or two (for scratchpad writes). Page 184 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 16.5. CCH0TN: Cache Tuning Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value CHMSCTL CHALGM CHFIXM CHMSTH 00000100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA2 SFR Page: F Bits 7-4: CHMSCTL: Cache Miss Penalty Accumulator (Bits 4-1). These are bits 4-1 of the Cache Miss Penalty Accumulator (See Figure 16.7). Bit 3: CHALGM: Cache Algorithm Select. This bit selects the cache replacement algorithm. 0: Cache uses Rebound algorithm. 1: Cache uses Pseudo-random algorithm. Bit 2: CHFIXM: Cache Fix MOVC Enable. This bit forces MOVC writes to the cache memory to use slot 0. 0: MOVC data is written according to the current algorithm selected by the CHALGM bit. 1: MOVC data is always written to cache slot 0. Bits 1-0: CHMSTH: Cache Miss Penalty Threshold. These bits determine when missed instruction data will be cached. If data takes longer than CHMSTH clocks to obtain, it will be cached. Figure 16.6. CCH0LC: Cache Lock Control Register R/W R/W R R R R R R Reset Value CHPUSH CHPOP CHSLOT 00111110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA3 SFR Page: F Bit 7: Bit 6: Bits 5-0: CHPUSH: Cache Push Enable. This bit enables cache push operations, which will lock information in cache slots using MOVC instructions. 0: Cache push operations are disabled. 1: Cache push operations are enabled. When a MOVC read is executed, the requested 4-byte segment containing the data is locked into the cache at the location indicated by CHSLOT, and CHSLOT is decremented. Note that no more than 61 cache slots should be locked at one time, since the entire cache will be unlocked when CHSLOT is equal to 0. CHPOP: Cache Pop. Writing a ‘1’ to this bit will increment CHSLOT and then unlock that location. This bit always reads ‘0’. Note that Cache Pop operations should not be performed while CHSLOT = 111110b. CHSLOT: Cache Slot Pointer. These read-only bits are the pointer into the cache lock stack. Locations above CHSLOT are locked, and will not be changed by the processor, except when CHSLOT equals 0. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 185
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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