Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Table 13.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS /RST Output Low Voltage I OL =8.5mA,VDD=2.7Vto3.6V 0.6 V /RST Input High Voltage 0.7 x VDD V /RST Input Low Voltage 0.3 x VDD /RST Input Leakage Current /RST = 0.0 V 50 µA VDD for /RST Output Valid 1.0 V AV+ for /RST Output Valid 1.0 V VDD POR Threshold (V RST ) 2.40 2.55 2.70 V Minimum /RST Low Time to Generate a System Reset 10 ns Reset Time Delay /RST rising edge after VDD crosses V RST threshold 80 100 120 ms Missing Clock Detector Timeout Time from last system clock to reset initiation 100 220 500 µs Page 160 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 14. OSCILLATORS C8051F120/1/2/3/4/5/6/7 devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled, disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 14.1. The system clock can be sourced by the external oscillator circuit, the internal oscillator, or the on-chip phase-locked loop (PLL). The internal oscillator's electrical specifications are given in Table 14.1 on page 163. Figure 14.1. Oscillator Diagram OSCICL OSCICN CLKSEL Option 3 XTAL1 XTAL2 IOSCEN IFRDY IFCN1 IFCN0 CLKDIV1 CLKDIV0 CLKSL1 CLKSL0 Option 2 VDD XTAL1 Option 4 XTAL1 Option 1 XTAL1 XTAL2 EN Calibrated Internal Oscillator Input Circuit OSC n 00 01 SYSCLK PLL 10 XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 OSCXCN 14.1. Programmable Internal Oscillator All C8051F12x devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by Figure 14.2. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. Electrical specifications for the precision internal oscillator are given in Table 14.1. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 161
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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