Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 14.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in Figure 14.5 (OSCXCN register). For example, an 11.0592 MHz crystal requires an XFCN setting of 111b. When the crystal oscillator is enabled, the oscillator amplitude detection circuit requires a settle time to achieve proper bias. Waiting at least 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock. Switching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior. The recommended procedure is: Step 1. Enable the external oscillator. Step 2. Wait at least 1 ms. Step 3. Poll for XTLVLD => ‘1’. Step 4. Switch the system clock to the external oscillator. Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference. 14.5. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation. If the frequency desired is 100 kHz, let R = 246 kΩ andC=50pF: f=1.23(10 3 )/RC=1.23(10 3 ) / [ 246 * 50 ] = 0.1 MHz = 100 kHz Referring to the table in Figure 14.5, the required XFCN setting is 010. 14.6. External Capacitor Example If a capacitor is used as an external oscillator for the MCU, the circuit should be configured as shown in Figure 14.1, Option 3. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, select the capacitor to be used and find the frequency of oscillation from the equations below. Assume VDD = 3.0 V and C = 50 pF: f = KF / ( C * VDD ) = KF / ( 50 * 3 ) f = KF / 150 If a frequency of roughly 50 kHz is desired, select the K Factor from the table in Figure 14.5 as KF = 7.7: f = 7.7 / 150 = 0.051 MHz, or 51 kHz Therefore, the XFCN value to use in this example is 010. Page 166 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 14.7. Phase-Locked Loop (PLL) The C8051F12x Family include a Phase-Locked-Loop (PLL), which is used to multiply the internal oscillator or an external clock source to achieve higher CPU operating frequencies. The PLL circuitry is designed to produce an output frequency between 25 MHz and 100 MHz, from a divided reference frequency between 5 MHz and 30 MHz. A block diagram of the PLL is shown in Figure 14.6. Figure 14.6. PLL Block Diagram PLL0CN PLL0FLT PLLM4 PLLM3 PLLM2 PLLM1 PLLM0 PLLN7 PLLN6 PLLN5 PLLN4 PLLN3 PLLN2 PLLN1 PLLN0 PLLLCK PLLSRC PLLEN PLLPWR PLLICO1 PLLICO0 PLLLP3 PLLLP2 PLLLP1 PLLLP0 Internal Oscillator External Oscillator 0 1 Divided Reference Clock Phase / ÷ Frequency Detection LoopFilter ÷ Current Controlled Oscillator PLL Clock Output PLL0DIV PLL0MUL 14.7.1. PLL Input Clock and Pre-divider The PLL circuitry can derive its reference clock from either the internal oscillator or an external clock source. The PLLSRC bit (PLL0CN.2) controls which clock source is used for the reference clock (see Figure 14.7). If PLLSRC is set to ‘0’, the internal oscillator source is used. Note that the internal oscillator divide factor (as specified by bits IFCN1-0 in register OSCICN) will also apply to this clock. When PLLSRC is set to ‘1’, an external oscillator source will be used. The external oscillator should be active and settled before it is selected as a reference clock for the PLL circuit. The reference clock is divided down prior to the PLL circuit, according to the contents of the PLLM4-0 bits in the PLL Pre-divider Register (PLL0DIV), shown in Figure 14.8. 14.7.2. PLL Multiplication and Output Clock The PLL circuitry will multiply the divided reference clock by the multiplication factor stored in the PLL0MUL register shown in Figure 14.9. To accomplish this, it uses a feedback loop consisting of a phase/frequency detector, a loop filter, and a current-controlled oscillator (ICO). It is important to configure the loop filter and the ICO for the correct frequency ranges. The PLLLP3-0 bits (PLL0FLT.3-0) should be set according to the divided reference clock frequency. Likewise, the PLLICO1-0 bits (PLL0FLT.5-4) should be set according to the desired output frequency range. Figure 14.10 describes the proper settings to use for the PLLLP3-0 and PLLICO1-0 bits. When the PLL is locked and stable at the desired frequency, the PLLLCK bit (PLL0CN.5) will be set to a ‘1’. The resulting PLL frequency will be set according to the equation: PLLN PLL Frequency = Reference Frequency × --------------- PLLM Where “Reference Frequency” is the selected source clock frequency, PLLN is the PLL Multiplier, and PLLM is the PLL Pre-divider. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 167
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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