Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 24.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate pulse width modulated (PWM) outputs on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register. When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be high. When the count value in PCA0L overflows, the CEXn output will be low (see Figure 24.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the counter/timer's high byte (PCA0H) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 24.2. Equation 24.2. 8-Bit PWM Duty Cycle DutyCycle ( 256 – PCA0CPHn) = -------------------------------------------------- 256 Figure 24.8. PCA 8-Bit PWM Mode Diagram PCA0CPHn PCA0CPMn P E C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F 6 n n n n n 0 0 0 0 0 0 PCA0CPLn Enable 8-bit Comparator match S SET Q CEXn Crossbar Port I/O R CLR Q PCA Timebase PCA0L Overflow Page 298 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 24.2.6. 16-Bit Pulse Width Modulator Mode Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle, CCFn should also be set to logic 1 to enable match interrupts. The duty cycle for 16-Bit PWM Mode is given by Equation 24.3. 16-Bit PWM Duty Cycle DutyCycle ( 65536 – PCA0CPn) = ---------------------------------------------------- 65536 Figure 24.9. PCA 16-Bit PWM Mode PCA0CPMn P E C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F 6 n n n n n 1 0 0 0 0 0 PCA0CPHn PCA0CPLn Enable 16-bit Comparator match S SET Q CEXn Crossbar Port I/O R CLR Q PCA Timebase PCA0H PCA0L Overflow © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 299
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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