Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

C8051F120/1/2/3
C8051F124/5/6/7
Preliminary
7.2.3. Settling Time Requirements
When the ADC2 input configuration is changed (i.e., a different MUX or PGA selection), a minimum tracking time is
required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resistance,
the ADC2 sampling capacitance, any external source resistance, and the accuracy required for the conversion.
Figure 7.3 shows the equivalent ADC2 input circuit. The required ADC2 settling time for a given settling accuracy
(SA) may be approximated by Equation 7.1. Note: An absolute minimum settling time of 800 ns required after any
MUX selection. Note that in low-power tracking mode, three SAR2 clocks are used for tracking at the start of every
conversion. For most applications, these three SAR2 clocks will meet the tracking requirements.
Equation 7.1. ADC2 Settling Time Requirements
t
=
2 n
ln⎛ ⎝
------ ⎞
SA⎠
× R TOTAL
C SAMPLE
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R TOTAL is the sum of the ADC2 MUX resistance and any external source resistance.
n is the ADC resolution in bits (8).
Figure 7.3. ADC2 Equivalent Input Circuit
Differential Mode
Single-Ended Mode
MUX Select
MUX Select
AIN2.x
R MUX
=5k
AIN2.x
R MUX
=5k
C SAMPLE
=5pF
C SAMPLE
=5pF
RC Input
=R MUX
*C SAMPLE
RC Input
=R MUX
*C SAMPLE
C SAMPLE
=5pF
AIN2.y
R MUX
=5k
MUX Select
Note:WhenthePGAgainissetto0.5,C SAMPLE
=3pF
Page 86
DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.