Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 12.7.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 12.4. 12.7.4. Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETIis executed, a single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETIinstruction followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Page 146 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 12.7.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). Figure 12.21. IE: Interrupt Enable Bit7: EA: Enable All Interrupts. This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings. 0: Disable all interrupt sources. 1: Enable each interrupt according to its individual mask setting. Bit6: IEGF0: General Purpose Flag 0. This is a general purpose flag for use under software control. Bit5: ET2: Enabler Timer 2 Interrupt. This bit sets the masking of the Timer 2 interrupt. 0: Disable Timer 2 interrupt. 1: Enable Timer 2 interrupt. Bit4: ES0: Enable UART0 Interrupt. This bit sets the masking of the UART0 interrupt. 0: Disable UART0 interrupt. Bit3: 1: Enable UART0 interrupt. ET1: Enable Timer 1 Interrupt. This bit sets the masking of the Timer 1 interrupt. 0: Disable Timer 1 interrupt. 1: Enable Timer 1 interrupt. Bit2: EX1: Enable External Interrupt 1. This bit sets the masking of External Interrupt 1. 0: Disable External Interrupt 1. 1: Enable External Interrupt 1. Bit1: R/W R/W R/W R/W R/W R/W R/W R/W Reset Value EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xA8 SFR Page: All Pages ET0: Enable Timer 0 Interrupt. This bit sets the masking of the Timer 0 interrupt. 0: Disable Timer 0 interrupts. 1: Enable Timer 0 interrupts. Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable External Interrupt 0. 1: Enable External Interrupt 0. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 147
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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