Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 20.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures. Figure 20.6. SPI0CFG: SPI0 Configuration Register R R/W R/W R/W R R R R Reset Value SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9A SFR Page: 0 Bit 7: Bit6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: SPIBSY: SPI Busy. This bit is set to logic 1 when a SPItransfer is in progress (Master or slave Mode). MSTEN:MasterModeEnable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. CKPHA: SPI0 Clock Phase. This bit controls the SPI0 clock phase. 0: Data sampled on first edge of SCK period. 1: Data sampled on second edge of SCK period. CKPOL: SPI0 Clock Polarity. This bit controls the SPI0 clock polarity. 0: SCK line low in idle state. 1: SCK line high in idle state. SLVSEL: Slave Selected Flag. This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input. NSSIN: NSS Instantaneous Pin Input. This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched. SRMT: Shift Register Empty (Valid in Slave Mode). This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK. NOTE: SRMT = 1 when in Master Mode. RXBMT: Receive Buffer Empty (Valid in Slave Mode). This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0. NOTE:RXBMT=1wheninMasterMode. Page 246 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 20.7. SPI0CN: SPI0 Control Register R/W R/W R/W R/W R/W R/W R R/W Reset Value SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN 00000100 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xF8 SFR Page: 0 Bit 7: Bit 6: Bit5: Bit 4: Bits 3-2: Bit1: Bit0: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software. WCOL: Write Collision Flag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. It must be cleared by software. MODF:ModeFaultFlag. This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software. RXOVRN: Receive Overrun Flag (Slave Mode only). This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software. NSSMD1-NSSMD0: Slave Select Mode. Selects between the following NSS operation modes: (See Section “20.2. SPI0 Master Mode Operation” on page 241 and Section “20.3. SPI0 Slave Mode Operation” on page 243). 00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin. 01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device. 1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will assume the value of NSSMD0. TXBMT:TransmitBufferEmpty. This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPIshift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. SPIEN:SPI0Enable. This bit enables/disables the SPI. 0: SPIdisabled. 1: SPIenabled. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 247
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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