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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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<strong>Preliminary</strong><br />

<strong>C8051F120</strong>/1/2/3<br />

<strong>C8051F124</strong>/5/6/7<br />

9. VOLTAGE REFERENCE (<strong>C8051F120</strong>/2/4/6)<br />

The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference<br />

input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage reference<br />

output. ADC0 may also reference the DAC0 output internally, and ADC2 may reference the analog power supply<br />

voltage, via the VREF multiplexers shown in Figure 9.1.<br />

The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator<br />

and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system<br />

components or to the voltage reference input pins shown in Figure 9.1. The maximum load seen by the VREF pin<br />

must be less than 200 µA to AGND. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to<br />

AGND, as shown in Figure 9.1.<br />

The Reference Control Register, REF0CN (defined in Figure 9.2) enables/disables the internal reference generator<br />

and selects the reference inputs for ADC0 and ADC2. The BIASE bit in REF0CN enables the on-board reference<br />

generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled,<br />

the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the<br />

buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator,<br />

BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0.<br />

Note that the BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether the voltage reference<br />

is derived from the on-chip reference or supplied by an off-chip source. If neither the ADC nor the DAC are<br />

being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD2VRS select the ADC0<br />

and ADC2 voltage reference sources, respectively. The electrical specifications for the Voltage Reference are given in<br />

Table 9.1.<br />

Figure 9.1. Voltage Reference Functional Block Diagram<br />

REF0CN<br />

AD0VRS<br />

AD2VRS<br />

TEMPE<br />

BIASE<br />

REFBE<br />

AV+<br />

1<br />

ADC2<br />

Ref<br />

VDD<br />

VREF2<br />

0<br />

External<br />

Voltage<br />

Reference<br />

Circuit<br />

R1<br />

ADC0<br />

DGND<br />

VREF0<br />

0<br />

Ref<br />

1<br />

VREFD<br />

DAC0<br />

Ref<br />

DAC1<br />

BIASE<br />

+<br />

4.7µF<br />

0.1µF<br />

VREF<br />

x2<br />

EN<br />

1.2V<br />

Band-Gap<br />

Bias to<br />

ADCs,<br />

DACs<br />

REFBE<br />

Recommended Bypass<br />

Capacitors<br />

© 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 105

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