Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary . Figure 14.2. OSCICL: Internal Oscillator Calibration Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8B SFR Page: F Bits 7-0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines the internal oscillator base frequency. The reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. Figure 14.3. OSCICN: Internal Oscillator Control Register R/W R R/W R R/W R/W R/W R/W Reset Value IOSCEN IFRDY - - - - IFCN1 IFCN0 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8A SFR Page: F Bit 7: Bit 6: Bits 5-2: Bits 1-0: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator not running at programmed frequency. 1: Internal Oscillator running at programmed frequency. Reserved. IFCN1-0: Internal Oscillator Frequency Control Bits. 00: Internal Oscillator is divided by 8. 01: Internal Oscillator is divided by 4. 10: Internal Oscillator is divided by 2. 11: Internal Oscillator is divided by 1. Page 162 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Table 14.1. Internal Oscillator Electrical Characteristics -40°C to +85°C unless otherwise specified PARAMETER CONDITIONS MIN TYP MAX UNITS Calibrated Internal Oscillator 24 24.5 25 MHz Frequency Internal Oscillator Supply Current OSCICN.7 = 1 TBD µA (from VDD) 14.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14.1. In RC, capacitor, or CMOS clock configuration, the clock source should be wired to the XTAL2 and/or XTAL1 pin(s) as shown in Option 2, 3, or 4 of Figure 14.1. The type of external oscillator must be selected in the OSCXCN register, and the frequency control bits (XFCN) must be selected appropriately (see Figure 14.5). 14.3. System Clock Selection The CLKSL1-0 bits in register CLKSEL select which oscillator source generates the system clock. CLKSL1-0 must be set to ‘01’ for the system clock to run from the external oscillator; however the external oscillator may still clock certain peripherals, such as the timers and PCA, when the internal oscillator or the PLL is selected as the system clock. The system clock may be switched on-the-fly between the internal and external oscillators or the PLL, so long as the selected oscillator source is enabled and settled. The internal oscillator requires little start-up time, and may be enabled and selected as the system clock in the same write to OSCICN. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use as the system clock. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘1’ by hardware when the external oscillator is settled. To avoid reading a false XTLVLD, in crystal mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD. RC and C modes typically require no startup time. The PLL also requires time to lock onto the desired frequency, and the PLL Lock Flag (PLLLCK in register PLL0CN) is set to ‘1’ by hardware once the PLL is locked on the correct frequency. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 163
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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