Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

More documents

Recommendations

Info

C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 18.16. P2MDOUT: Port2 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA6 SFR Page: F Bits7-0: Note: P2MDOUT.[7:0]: Port2 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are always configured as Open-Drain when they appear on Port pins. Figure 18.17. P3: Port3 Data Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 11111111 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xB0 SFR Page: All Pages Bits7-0: Note: P3.[7:0]: Port3 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers) 0: Logic Low Output. 1: Logic High Output (open if corresponding P3MDOUT.n bit = 0). (Read - Regardless of XBR0, XBR1, and XBR2 Register settings). 0: P3.n pin is logic low. 1: P3.n pin is logic high. P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed mode, or as D[7:0] in Non-multiplexed mode). See Section “17. EXTERNAL DATA MEMORY INTER- FACE AND ON-CHIP XRAM” on page 187 for more information about the External Memory Interface. Page 218 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 18.18. P3MDOUT: Port3 Output Mode Register R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA7 SFR Page: F Bits7-0: P2MDOUT.[7:0]: Port3 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. 18.2. Ports 4 through 7 (C8051F120/2/4/6 only) All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 18.19, Figure 18.21, Figure 18.23, and Figure 18.25), a set of SFR’s which are both bit and byte-addressable. A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV operation). During the read cycle of the read-modify-write instruction, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read. 18.2.1. Configuring Ports which are not Pinned Out Although P4, P5, P6, and P7 are not brought out to pins on the C8051F121/3/5/7 devices, the Port Data registers are still present and can be used by software. Because the digital input paths also remain active, it is recommended that these pins not be left in a ‘floating’ state in order to avoid unnecessary power dissipation arising from the inputs floating to non-valid logic levels. This condition can be prevented by any of the following: 1. Leave the weak pull-up devices enabled by setting WEAKPUD (XBR2.7) to a logic 0. 2. Configure the output modes of P4, P5, P6, and P7 to “Push-Pull” by writing PnOUT = 0xFF. 3. Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data registers: P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00. 18.2.2. Configuring the Output Modes of the Port Pins The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a highimpedance state. The Open-Drain configuration is useful to prevent contention between devices in systems where the Port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire. The output modes of the Port pins on Ports 4 through 7 are determined by the bits in their respective PnMDOUT Output Mode Registers. Each bit in PnMDOUT controls the output mode of its corresponding port pin (see Figure 18.20, Figure 18.22, Figure 18.24, and Figure 18.26). For example, to place Port pin 4.3 in push-pull mode (digital output), set P4MDOUT.3 to logic 1. All port pins default to open-drain mode upon device reset. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 219
Page 1 and 2:
Preliminary C8051F120/1/2/3 C8051F1
Page 3 and 4:
Page 5 and 6:
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
Page 15 and 16:
Page 17 and 18:
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
© 2002 Cygnal Integrated Products,
Page 45 and 46:
© 2002 Cygnal Integrated Products,
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
Page 107 and 108:
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
Page 135 and 136:
Page 137 and 138:
Page 139 and 140:
Page 141 and 142:
Page 143 and 144:
Page 145 and 146:
Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Page 153 and 154:
Page 155 and 156:
Page 157 and 158:
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168: Preliminary C8051F120/1/2/3 C8051F1
Page 217: Preliminary C8051F120/1/2/3 C8051F1
Page 269 and 270:
Page 271 and 272:
Page 273 and 274:
Page 275 and 276:
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
show all

Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?