Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 1.1.3. Additional Features The C8051F12x MCU family includes several key enhancements to the CIP-51 core and peripherals to improve overall performance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building multi-tasking, real-time systems. There are up to seven reset sources for the MCU: an on-board VDD monitor, a Watchdog Timer, a missing clock detector, a voltage level detection from Comparator0, a forced software reset, the CNVSTR0 input pin, and the /RST pin. The /RST pin is bi-directional, accommodating an external reset, or allowing the internally generated POR to be output on the /RST pin. Each reset source except for the VDD monitor and Reset Input pin may be disabled by the user in software; the VDD monitor is enabled/disabled via the MONEN pin. The Watchdog Timer may be permanently enabled in software after a power-on reset during MCU initialization. The MCU has an internal, stand alone clock generator which is used by default as the system clock after any reset. If desired, the clock source may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, RC, or external clock source to generate the system clock. This can be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) external crystal source, while periodically switching to the 24.5 MHz internal oscillator as needed. Additionally, an on-chip PLL is provided to achieve higher system clock speeds for increased throughput. Figure 1.5. On-Board Clock and Reset VDD (Port I/O) CP0+ CP0- Crossbar CNVSTR (CNVSTR reset enable) Comparator0 + - (CP0 reset enable) Supply Monitor + - Supply Reset Timeout (wired-OR) /RST Internal Clock Generator Missing Clock Detector (oneshot) EN MCD Enable WDT Enable WDT EN PRE WDT Strobe Reset Funnel XTAL1 XTAL2 PLL Circuitry OSC System Clock Clock Select CIP-51 Microcontroller Core Software Reset System Reset Extended Interrupt Handler Page 26 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. The CIP-51 in the C8051F12x MCUs additionally has an on-chip 8k byte RAM block and an external memory interface (EMIF) for accessing off-chip data memory. The on-chip 8k byte block can be addressed over the entire 64k external data memory address range (overlapping 8k boundaries). External data memory address space can be mapped to on-chip memory only, off-chip memory only, or a combination of the two (addresses up to 8k directed to on-chip, above 8k directed to EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. The MCU’s program memory consists of 128k bytes of banked FLASH memory. This memory may be reprogrammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage. The 1024 bytes from addresses 0x1FC00 to 0x1FFFF are reserved. There are also two 128 byte sectors at addresses 0x20000 to 0x200FF, which may be used by software. See Figure 1.6 for the MCU system memory map. Figure 1.6. On-Chip Memory Map 0x200FF 0x20000 0x1FFFF 0x1FC00 0x1FBFF 0x00000 PROGRAM/DATA MEMORY (FLASH) Scrachpad Memory (DATA only) RESERVED FLASH (In-System Programmable in 1024 Byte Sectors) 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 0xFFFF DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers Special Function Registers (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) EXTERNAL DATA ADDRESS SPACE 0 1 2 3 Up To 256 SFR Pages Off-chipXRAM space 0x2000 0x1FFF 0x0000 XRAM - 8192 Bytes (accessable using MOVX instruction) © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 27
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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