Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 12.7. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 20 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.) Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR. However, most are not cleared by the hardware and must be cleared by software before returning from the ISR. If an interruptpending flag remains set after the CPU completes the return-from-interrupt (RETI) instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after the completion of the next instruction. 12.7.1. MCU Interrupt Sources and Vectors The MCUs support 20 interrupt sources. Software can simulate an interrupt event by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 12.4. Refer to the datasheet section associated with a particular onchip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). 12.7.2. External Interrupts Two of the external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or active-low edge-sensitive inputs depending on the setting of bits IT0 (TCON.0) and IT1 (TCON.2). IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin. The external interrupt source must hold the input active until the interrupt request is recognized. It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be generated. Page 144 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Interrupt Source Interrupt Vector Table 12.4. Interrupt Summary Priority Order Pending Flag Bit addressable? Cleared by HW? Enable Flag Priority Control Reset 0x0000 Top None N/A N/A Always Always Enabled Highest External Interrupt 0 (/INT0) 0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0) Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1) External Interrupt 1 (/INT1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2) Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3) UART0 0x0023 4 RI0 (SCON0.0) TI0 (SCON0.1) Y ES0 (IE.4) PS0 (IP.4) Timer 2 0x002B 5 TF2 (TMR2CN.7) EXF2 (TMR2CN.6) Y ET2 (IE.5) PT2 (IP.5) Serial Peripheral Interface 0x0033 6 SPIF (SPI0CN.7) Y ESPI0 PSPI0 (EIE1.0) (EIP1.0) SMBus Interface 0x003B 7 SI (SMB0CN.3) Y ESMB0 PSMB0 (EIE1.1) (EIP1.1) ADC0 Window Comparator 0x0043 8 AD0WINT EWADC0 PWADC0 Y (ADC0CN.1) (EIE1.2) (EIP1.2) PCA 0 0x004B 9 CF (PCA0CN.7) EPCA0 PPCA0 Y CCFn (PCA0CN.n) (EIE1.3) (EIP1.3) Comparator 0 0x0053 10 CP0FIF ECP0F PCP0F Y (CPT0CN.4) (EIE1.4) (EIP1.4) Comparator 0 0x005B 11 CP0RIF ECP0R PCP0R Y (CPT0CN.5) (EIE1.5) (EIP1.5) Comparator 1 0x0063 12 CP1FIF ECP1F PCP1F Y (CPT1CN.4) (EIE1.6) (EIP1.6) Comparator 1 0x006B 13 CP1RIF ECP1R PCP1F Y (CPT1CN.5) (EIE1.7) (EIP1.7) Timer 3 0x0073 14 TF3 (TMR3CN.7) ET3 PT3 Y EXF3 (TMR3CN.6) (EIE2.0) (EIP2.0) ADC0 End of Conversion 0x007B 15 AD0INT EADC0 PADC0 Y (ADC0CN.5) (EIE2.1) (EIP2.1) Timer 4 0x0083 16 TF4 (TMR4CN.7) ET4 PT4 Y EXF4 (TMR4CN.7) (EIE2.2) (EIP2.2) ADC2 Window Comparator 0x008B 17 AD2WINT EWADC2 PWADC2 Y (ADC2CN.0) (EIE2.3) (EIP2.3) ADC2 End of Conversion 0x0093 18 AD2INT EADC2 PADC2 Y (ADC2CN.5) (EIE2.4) (EIP2.4) UART1 0x00A3 20 RI1 (SCON1.0) TI1 (SCON1.1) Y ES1 (EIE2.6) PS1 (EIP2.6) © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 145
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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