Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Notes Page 264 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 22. UART1 UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “22.1. Enhanced Baud Rate Generation” on page 266). Received data buffering allows UART1 to start reception of a second incoming data byte before software has finished reading the previous data byte. UART1 has two associated SFRs: Serial Control Register 1 (SCON1) and Serial Data Buffer 1 (SBUF1). The single SBUF1 location provides access to both transmit and receive registers. Reading SBUF1 accesses the buffered Receive register; writing SBUF1 accesses the Transmit register. With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive complete). Figure 22.1. UART1 Block Diagram SFR Bus Write to SBUF1 TB81 SET D Q CLR SBUF1 (TX Shift) TX1 Crossbar Zero Detector StopBit Shift Data Start Tx Clock Tx Control Tx IRQ Send UART1 Baud Rate Generator S1MODE SCON1 MCE1 REN1 TB81 RB81 TI1 RI1 TI1 RI1 Serial Port Interrupt Port I/O Rx Clock Start Rx Control Shift 0x1FF RB81 Rx IRQ Load SBUF1 Input Shift Register (9 bits) Load SBUF1 SBUF1 (RX Latch) Read SBUF1 SFR Bus RX1 Crossbar © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 265
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