Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 23.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers R/W R/W R/W R/W R/W Reset Value - - - TnM1 TnM0 TOGn TnOE DCEN 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: TMR2CF:0xC9;TMR3CF:0xC9;TMR4CF:0xC9 SFR Page TMR2CF: page 0;TMR3CF: page 1;TMR4CF: Page 2 Bit Addressable Bit7-5: Bit4-3: Bit2: Bit1: Bit0: Reserved. TnM1 and TnM0: Timer Clock Mode Select Bits. Bits used to select the Timer clock source. The sources can be the System Clock (SYSCLK), SYSCLK divided by 2 or 12, or the external clock divided by 8. Clock source is selected as follows: 00: SYSCLK/12 01: SYSCLK 10: EXTERNAL CLOCK/8 (Synchronized to the System Clock) 11: SYSCLK/2 TOGn: Toggle output state bit. When timer is used to toggle a port pin, this bit can be used to read the state of the output, or can be written to in order to force the state of the output (Timer 2 and Timer 4 Only). TnOE: Timer output enable bit. This bit enables the timer to output a 50% duty cycle output to the timer’s assigned external port pin. NOTE: A timer is configured for Square Wave Output as follows: CP/RLn = 0 C/Tn = 1 TnOE= 1 Load RCAPnH:RCAPnL (See “Square Wave Frequency (Timer 2 and Timer 4 Only)” on page 286.) Configure Port Pin to output squarewave (See Section “18. PORT INPUT/OUTPUT” on page 203) 0: Output of toggle mode not available at Timers’s assigned port pin. 1: Output of toggle mode available at Timers’s assigned port pin. DCEN: Decrement Enable Bit. This bit enables the timer to count up or down as determined by the state of TnEX. 0: Timer will count up, regardless of the state of TnEX. 1: Timer will count up or down depending on the state of TnEX as follows: if TnEX = 0, the timer counts DOWN. if TnEX = 1, the timer counts UP. Note: Timer 3 and Timer 2 share the T2 and T2EX pins. Page 288 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 23.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: RCAP2L: 0xCA; RCAP3L: 0xCA; RCAP4L: 0xCA SFR Page: RCAP2L: page 0; RCAP3L: page 1; RCAP4L: page 2 Bits 7-0: RCAP2, 3, and 4L: Timer 2, 3, and 4 Capture Register Low Byte. The RCAP2, 3, and 4L register captures the low byte of Timer 2, 3, and 4 when Timer 2, 3, and 4 is configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload mode, it holds the low byte of the reload value. Figure 23.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: RCAP2H: 0xCB; RCAP3H: 0xCB; RCAP4H: 0xCB SFR Page: RCAP2H: page 0; RCAP3H: page 1; RCAP4H: page 2 Bits 7-0: RCAP2, 3, and 4H: Timer 2, 3, and 4 Capture Register High Byte. The RCAP2, 3, and 4H register captures the highballed of Timer 2, 3, and 4 when Timer 2, 3, and 4 is configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload mode, it holds the high byte of the reload value. Figure 23.17. TMRnL: Timer 2, 3, and 4 Low Byte R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: TMR2L: 0xCC; TMR3L: 0xCC; TMR4L: 0xCC SFRPage:TMR2L:page0;TMR3L:page1;TMR4L:page2 Bits 7-0: TL2, 3, and 4: Timer 2, 3, and 4 Low Byte. The TL2, 3, and 4 register contains the low byte of the 16-bit Timer 2, 3, and 4 © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 289
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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