Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 18.1.5. Configuring Port 1 Pins as Analog Inputs ...........................................................207 18.1.6. External Memory Interface Pin Assignments......................................................208 18.1.7. Crossbar Pin Assignment Example......................................................................210 18.2.Ports 4 through 7 (C8051F120/2/4/6 only) ...................................................................219 18.2.1. Configuring Ports which are not Pinned Out.......................................................219 18.2.2. Configuring the Output Modes of the Port Pins ..................................................219 18.2.3. Configuring Port Pins as Digital Inputs...............................................................220 18.2.4. Weak Pull-ups......................................................................................................220 18.2.5. External Memory Interface..................................................................................220 19. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................225 19.1.Supporting Documents ..................................................................................................227 19.2.SMBus Protocol.............................................................................................................227 19.2.1. Arbitration............................................................................................................227 19.2.2. Clock Low Extension...........................................................................................228 19.2.3. SCL Low Timeout ...............................................................................................228 19.2.4. SCL High (SMBus Free) Timeout.......................................................................228 19.3.SMBus Transfer Modes.................................................................................................229 19.3.1. Master Transmitter Mode ....................................................................................229 19.3.2. Master Receiver Mode.........................................................................................229 19.3.3. Slave Transmitter Mode.......................................................................................230 19.3.4. Slave Receiver Mode ...........................................................................................230 19.4.SMBus Special Function Registers ...............................................................................231 19.4.1. Control Register...................................................................................................231 19.4.2. Clock Rate Register .............................................................................................233 19.4.3. Data Register........................................................................................................234 19.4.4. Address Register ..................................................................................................234 19.4.5. Status Register .....................................................................................................235 20. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................239 20.1.Signal Descriptions........................................................................................................240 20.1.1. Master Out, Slave In (MOSI) ..............................................................................240 20.1.2. Master In, Slave Out (MISO) ..............................................................................240 20.1.3. Serial Clock (SCK) ..............................................................................................240 20.1.4. Slave Select (NSS)...............................................................................................240 20.2.SPI0 Master Mode Operation........................................................................................241 20.3.SPI0 Slave Mode Operation ..........................................................................................243 20.4.SPI0 Interrupt Sources...................................................................................................244 20.5.Serial Clock Timing ......................................................................................................245 20.6.SPISpecial Function Registers .....................................................................................246 21. UART0 ..................................................................................................................................253 21.1.UART0 Operational Modes ..........................................................................................254 21.1.1. Mode 0: Synchronous Mode................................................................................254 21.1.2. Mode 1: 8-Bit UART, Variable Baud Rate .........................................................255 21.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate ..............................................................256 21.1.4. Mode 3: 9-Bit UART, Variable Baud Rate .........................................................257 21.2.Multiprocessor Communications...................................................................................258 Page 6 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 21.2.1. Configuration of a Masked Address ....................................................................258 21.2.2. Broadcast Addressing ..........................................................................................258 21.3.Frame and Transmission Error Detection......................................................................259 22. UART1 ..................................................................................................................................265 22.1.Enhanced Baud Rate Generation...................................................................................266 22.2.Operational Modes ........................................................................................................267 22.2.1. 8-Bit UART .........................................................................................................267 22.2.2. 9-Bit UART .........................................................................................................268 22.3.Multiprocessor Communications...................................................................................269 23. TIMERS................................................................................................................................275 23.1.Timer 0 and Timer 1......................................................................................................275 23.1.1. Mode 0: 13-bit Counter/Timer.............................................................................275 23.1.2. Mode 1: 16-bit Counter/Timer.............................................................................276 23.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload.................................................277 23.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) ...........................................278 23.2.Timer 2, Timer 3, and Timer 4......................................................................................283 23.2.1. Configuring Timer 2, 3, and 4 to Count Down....................................................283 23.2.2. Capture Mode ......................................................................................................284 23.2.3. Auto-Reload Mode ..............................................................................................285 23.2.4. Toggle Output Mode (Timer 2 and Timer 4 Only)..............................................285 24. PROGRAMMABLE COUNTER ARRAY .......................................................................291 24.1.PCA Counter/Timer.......................................................................................................292 24.2.Capture/Compare Modules............................................................................................293 24.2.1. Edge-triggered Capture Mode .............................................................................294 24.2.2. Software Timer (Compare) Mode........................................................................295 24.2.3. High Speed Output Mode ....................................................................................296 24.2.4. Frequency Output Mode ......................................................................................297 24.2.5. 8-Bit Pulse Width Modulator Mode ....................................................................298 24.2.6. 16-Bit Pulse Width Modulator Mode ..................................................................299 24.3.Register Descriptions for PCA0 ....................................................................................300 25. JTAG (IEEE 1149.1)............................................................................................................305 25.1.Boundary Scan...............................................................................................................306 25.1.1. EXTEST Instruction ............................................................................................307 25.1.2. SAMPLE Instruction ...........................................................................................307 25.1.3. BYPASS Instruction ............................................................................................307 25.1.4. IDCODE Instruction ............................................................................................307 25.2.Flash Programming Commands ....................................................................................308 25.3.Debug Support...............................................................................................................312 © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 7
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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