Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 24.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-tohigh transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Figure 24.4. PCA Capture Mode Diagram PCA Interrupt PCA0CPMn P E C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F 6 n n n n n PCA0CN C C C C C C C C F R C C C C C C F F F F F F 5 4 3 2 1 0 Port I/O Crossbar CEXn 0 1 0 (to CCFn) Capture PCA0CPLn PCA0CPHn 1 PCA Timebase PCA0L PCA0H Note: The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid. Page 294 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 24.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA0 counter/timer is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software Timer mode. Figure 24.5. PCA Software Timer Mode Diagram Write to PCA0CPLn Reset Write to PCA0CPHn 0 ENB ENB 1 PCA0CPMn P E C C M T P E W C A A A O W C M O P P T G M C 1 M P N n n n F 6 n n n n n x 0 0 0 0 x PCA0CPLn PCA0CPHn PCA Interrupt PCA0CN C C C C C C C C F R C C C C C C F F F F F F 5 4 3 2 1 0 Enable 16-bit Comparator Match 0 1 PCA Timebase PCA0L PCA0H © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 295
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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