Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 21.3. UART0 Mode 0 Interconnect............................................................................254 Figure 21.4. UART0 Mode 1 Timing Diagram .....................................................................255 Figure 21.5. UART0 Modes 2 and 3 Timing Diagram..........................................................256 Figure 21.6. UART0 Modes 1, 2, and 3 Interconnect Diagram ............................................257 Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................................259 Figure 21.8. SCON0: UART0 Control Register....................................................................261 Figure 21.9. SSTA0: UART0 Status and Clock Selection Register......................................262 Figure 21.10. SBUF0: UART0 Data Buffer Register............................................................263 Figure 21.11. SADDR0: UART0 Slave Address Register ....................................................263 Figure 21.12. SADEN0: UART0 Slave Address Enable Register ........................................263 22. UART1 ..................................................................................................................................265 Figure 22.1. UART1 Block Diagram.....................................................................................265 Figure 22.2. UART1 Baud Rate Logic ..................................................................................266 Figure 22.3. UART Interconnect Diagram ............................................................................267 Figure 22.4. 8-Bit UART Timing Diagram ...........................................................................267 Figure 22.5. 9-Bit UART Timing Diagram ...........................................................................268 Figure 22.6. UART Multi-Processor Mode Interconnect Diagram .......................................269 Figure 22.7. SCON1: Serial Port 1 Control Register.............................................................270 Figure 22.8. SBUF1: Serial (UART1) Port Data Buffer Register .........................................271 23. TIMERS................................................................................................................................275 Figure 23.1. T0 Mode 0 Block Diagram................................................................................276 Figure 23.2. T0 Mode 2 Block Diagram................................................................................277 Figure 23.3. T0 Mode 3 Block Diagram................................................................................278 Figure 23.4. TCON: Timer Control Register.........................................................................279 Figure 23.5. TMOD: Timer Mode Register...........................................................................280 Figure 23.6. CKCON: Clock Control Register......................................................................281 Figure 23.7. TL0: Timer 0 Low Byte ....................................................................................282 Figure 23.8. TL1: Timer 1 Low Byte ....................................................................................282 Figure 23.9. TH0: Timer 0 High Byte ...................................................................................282 Figure 23.10. TH1: Timer 1 High Byte .................................................................................282 Figure 23.11. T2, 3, and 4 Capture Mode Block Diagram ....................................................284 Figure 23.12. T2, 3, and 4 Auto-reload Mode Block Diagram..............................................285 Figure 23.13. TMRnCN: Timer 2, 3, and 4 Control Registers ..............................................287 Figure 23.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers ....................................288 Figure 23.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte................................289 Figure 23.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte ..............................289 Figure 23.17. TMRnL: Timer 2, 3, and 4 Low Byte .............................................................289 Figure 23.18. TMRnH Timer 2, 3, and 4 High Byte .............................................................290 24. PROGRAMMABLE COUNTER ARRAY .......................................................................291 Figure 24.1. PCA Block Diagram..........................................................................................291 Figure 24.2. PCA Counter/Timer Block Diagram.................................................................292 Figure 24.3. PCA Interrupt Block Diagram...........................................................................293 Figure 24.4. PCA Capture Mode Diagram ............................................................................294 Figure 24.5. PCA Software Timer Mode Diagram................................................................295 Figure 24.6. PCA High Speed Output Mode Diagram ..........................................................296 Page 14 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 24.7. PCA Frequency Output Mode...........................................................................297 Figure 24.8. PCA 8-Bit PWM Mode Diagram ......................................................................298 Figure 24.9. PCA 16-Bit PWM Mode ...................................................................................299 Figure 24.10. PCA0CN: PCA Control Register ....................................................................300 Figure 24.11. PCA0MD: PCA0 Mode Register ....................................................................301 Figure 24.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers .................................302 Figure 24.13. PCA0L: PCA0 Counter/Timer Low Byte .......................................................303 Figure 24.14. PCA0H: PCA0 Counter/Timer High Byte ......................................................303 Figure 24.15. PCA0CPLn: PCA0 Capture Module Low Byte ..............................................304 Figure 24.16. PCA0CPHn: PCA0 Capture Module High Byte.............................................304 25. JTAG (IEEE 1149.1)............................................................................................................305 Figure 25.1. IR: JTAG Instruction Register ..........................................................................305 Figure 25.2. DEVICEID: JTAG Device ID Register ............................................................307 Figure 25.3. FLASHCON: JTAG Flash Control Register.....................................................309 Figure 25.4. FLASHDAT: JTAG Flash Data Register..........................................................310 Figure 25.5. FLASHADR: JTAG Flash Address Register....................................................310 Figure 25.6. FLASHSCL: JTAG Flash Scale Register .........................................................311 © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 15
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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