Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary 4. PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions Name Pin Numbers F120/ 2/4/6 F121/ 3/5/7 Type Description VDD 37, 64, 90 DGND 38, 63, 89 24, 41, 57 25, 40, 56 Digital Supply Voltage. Must be tied to +2.7 to +3.6 V. Digital Ground. Must be tied to Ground. AV+ 11, 14 6 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. AGND 10, 13 5 Analog Ground. Must be tied to Ground. TMS 1 58 D In JTAG Test Mode Select with internal pull-up. TCK 2 59 D In JTAG Test Clock with internal pull-up. TDI3 60 D In JTAG Test Data Input with internal pull-up. TDIis latched on the rising edge of TCK. TDO 4 61 D Out JTAG Test Data Output with internal pull-up. Data is shifted out on TDO on the falling edge of TCK. TDO output is a tri-state driver. /RST 5 62 D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven low when VDD is < V RST and MONEN is high. An external source can initiate a system reset by driving this pin low. XTAL1 26 17 A In Crystal Input. This pin is the return for the internal oscillator circuit for a crystal or ceramic resonator. For a precision internal clock, connect a crystal or ceramic resonator from XTAL1 to XTAL2. If overdriven by an external CMOS clock, this becomes the system clock. XTAL2 27 18 A Out Crystal Output. This pin is the excitation driver for a crystal or ceramic resonator. MONEN 28 19 D In VDD Monitor Enable. When tied high, this pin enables the internal VDD monitor, which forces a system reset when VDD is < V RST . When tied low, the internal VDD monitor is disabled. This pin must be tied high or low. VREF 12 7 A I/O Bandgap Voltage Reference Output (all devices). DAC Voltage Reference Input (C8051F121/3/5/7 only). VREFA 8 A In ADC0 and ADC2 Voltage Reference Input. VREF0 16 A In ADC0 Voltage Reference Input. VREF2 17 A In ADC2 Voltage Reference Input. VREFD 15 A In DAC Voltage Reference Input. Page 38 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Name Pin Numbers F120/ 2/4/6 F121/ 3/5/7 Table 4.1. Pin Definitions Type Description AIN0.0 18 9 A In ADC0 Input Channel 0 (See ADC0 Specification for complete description). AIN0.1 19 10 A In ADC0 Input Channel 1 (See ADC0 Specification for complete description). AIN0.2 20 11 A In ADC0 Input Channel 2 (See ADC0 Specification for complete description). AIN0.3 21 12 A In ADC0 Input Channel 3 (See ADC0 Specification for complete description). AIN0.4 22 13 A In ADC0 Input Channel 4 (See ADC0 Specification for complete description). AIN0.5 23 14 A In ADC0 Input Channel 5 (See ADC0 Specification for complete description). AIN0.6 24 15 A In ADC0 Input Channel 6 (See ADC0 Specification for complete description). AIN0.7 25 16 A In ADC0 Input Channel 7 (See ADC0 Specification for complete description). CP0+ 9 4 A In Comparator 0 Non-Inverting Input. CP0- 8 3 A In Comparator 0 Inverting Input. CP1+ 7 2 A In Comparator 1 Non-Inverting Input. CP1- 6 1 A In Comparator 1 Inverting Input. DAC0 100 64 A Out Digital to Analog Converter 0 Voltage Output. (See DAC Specification for complete description). DAC1 99 63 A Out Digital to Analog Converter 1 Voltage Output. (See DAC Specification for complete description). P0.0 62 55 D I/O Port 0.0. See Port Input/Output section for complete description. P0.1 61 54 D I/O Port 0.1. See Port Input/Output section for complete description. P0.2 60 53 D I/O Port 0.2. See Port Input/Output section for complete description. P0.3 59 52 D I/O Port 0.3. See Port Input/Output section for complete description. P0.4 58 51 D I/O Port 0.4. See Port Input/Output section for complete description. ALE/P0.5 57 50 D I/O ALE Strobe for External Memory Address bus (multiplexed mode) Port 0.5 See Port Input/Output section for complete description. © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 39
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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