Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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C8051F120/1/2/3 C8051F124/5/6/7 Preliminary Figure 7.5. AMX2SL: AMUX2 Channel Select Register SFR Page: SFR Address: 2 0xBB R/W R/W R/W R/W R/W R/W R/W R/W Reset Value - - - - AMX2AD2 AMX2AD1 AMX2AD0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-3: Bits2-0: UNUSED. Read = 00000b; Write = don’t care. AMX2AD2-0: AMX2 Address Bits. 000-111b: ADC Inputs selected per chart below. AMX2CF Bits 3-0 AMX2AD2-0 000 001 010 011 100 101 110 111 0000 AIN2.0 AIN2.1 AIN2.2 AIN2.3 AIN2.4 AIN2.5 AIN2.6 AIN2.7 +(AIN2.0) 0001 AIN2.2 AIN2.3 AIN2.4 AIN2.5 AIN2.6 AIN2.7 -(AIN2.1) 0010 AIN2.0 AIN2.1 0011 +(AIN2.0) -(AIN2.1) +(AIN2.2) -(AIN2.3) +(AIN2.2) -(AIN2.3) 0100 AIN2.0 AIN2.1 AIN2.2 AIN2.3 0101 +(AIN2.0) -(AIN2.1) 0110 AIN2.0 AIN2.1 0111 +(AIN2.0) -(AIN2.1) AIN2.2 +(AIN2.2) -(AIN2.3) +(AIN2.2) -(AIN2.3) AIN2.3 AIN2.4 AIN2.5 AIN2.6 AIN2.7 AIN2.4 AIN2.5 AIN2.6 AIN2.7 +(AIN2.4) -(AIN2.5) +(AIN2.4) -(AIN2.5) +(AIN2.4) -(AIN2.5) +(AIN2.4) -(AIN2.5) 1000 AIN2.0 AIN2.1 AIN2.2 AIN2.3 AIN2.4 AIN2.5 1001 +(AIN2.0) -(AIN2.1) 1010 AIN2.0 AIN2.1 1011 +(AIN2.0) -(AIN2.1) AIN2.2 AIN2.3 AIN2.4 AIN2.5 +(AIN2.2) -(AIN2.3) +(AIN2.2) -(AIN2.3) 1100 AIN2.0 AIN2.1 AIN2.2 AIN2.3 1101 +(AIN2.0) -(AIN2.1) 1110 AIN2.0 AIN2.1 1111 +(AIN2.0) -(AIN2.1) AIN2.2 +(AIN2.2) -(AIN2.3) +(AIN2.2) -(AIN2.3) AIN2.3 AIN2.4 AIN2.4 +(AIN2.4) -(AIN2.5) +(AIN2.4) -(AIN2.5) +(AIN2.4) -(AIN2.5) +(AIN2.4) -(AIN2.5) AIN2.5 AIN2.5 AIN2.6 AIN2.6 AIN2.6 AIN2.6 +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) +(AIN2.6) -(AIN2.7) AIN2.7 AIN2.7 AIN2.7 AIN2.7 Page 88 DS008-0.8-AUG02 © 2002 Cygnal Integrated Products, Inc.
Preliminary C8051F120/1/2/3 C8051F124/5/6/7 Figure 7.6. ADC2CF: ADC2 Configuration Register SFR Page: SFR Address: 2 0xBC R/W R/W R/W R/W R/W R/W R/W R/W Reset Value AD2SC4 AD2SC3 AD2SC2 AD2SC1 AD2SC0 - AMP2GN1 AMP2GN0 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bits7-3: Bit2: Bits1-0: AD2SC4-0: ADC2 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD2SC refers to the 5-bit value held in AD2SC4-0, and CLK SAR2 refers to the desired ADC2 SAR clock (Note: the ADC2 SAR Conversion Clock should be less than or equal to 7.5 MHz). AD2SC = SYSCLK ---------------------- – 1 CLK SAR2 UNUSED. Read = 0b; Write = don’t care. AMP2GN1-0: ADC2 Internal Amplifier Gain (PGA). 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 © 2002 Cygnal Integrated Products, Inc. DS008-0.8-AUG02 Page 89
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Preliminary C8051F120/1/2/3 C8051F124/5/6/7 - KEMT FEI TUKE

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