Advanced POWER Virtualization on IBM System p5 - Previous ...

Traditional performance measurements were based on sampling, typically with a
100 Hz sample rate (each sample corresponds to a 10ms tic). Each sample is
sorted into one of four categories:
user
The interrupted code is outside the AIX 5L kernel.
sys
iowait
idle
The interrupted code is inside the AIX 5L kernel and the
currently running thread is not waitproc.
The currently running thread is waitproc and there is an
I/O pending.
The currently running thread is waitproc and there is no
I/O pending.
This traditional mechanism must stay unchanged to preserve binary compatibility
with earlier tools.
This sampling-based approach breaks down in a virtualized environment, as the
assumption that the dispatch cycle of each virtual processor is the same no
longer holds true. A similar problem exists with SMT; if one thread is consuming
100 percent of the time on a physical CPU, sample-based reporting would report
the system 50 percent busy (one processor at 100 percent, the other at 0
percent), but in fact the processor is really 100 percent busy.
5.5.2 Process Utilization Resource Register (PURR)
The PURR is simply a 64-bit counter with the same units for the timebase and
decrementer registers that provide per-thread processor utilization statistics.
Figure 5-24 on page 323 shows the logical CPUs and the relationship of the
PURR registers within a single <strong>POWER</strong>5 processor (core) and the two hardware
threads. With SMT enabled, each hardware thread is seen as a logical
processor.
The timebase register shown in Figure 5-24 on page 323 is simply a hardware
register that is incremented at each tic. The decrementer register provides
periodic interrupts.
322 <strong>Advanced</strong> <strong>POWER</strong> <strong>Virtualization</strong> on IBM System p5