Third Day Poster Session, 17 June 2010 - NanoTR-VI

Poster Session, Thursday, June 17
Theme F686 - N1123
Routing Congestion Removing of Nano/CMOS FPGA circuits
Hossein Hamidipour 1 , Parviz Keshavarzi 1 and Ali Naderi 1,*
1 Electrical and Computer Engineering Faculty, Semnan University, Semnan, Iran
Abstract CMOS Molecular (CMOL) architecture basically called hybrid nanowire/ molecular/ semiconductor circuit
which incorporates the nanodevices and nanowires crossbar into the CMOS IC implementation. CMOL technology uses the
advantages of nano and CMOS technology together. In this paper we have proposed a recursive method for removing the
routing congestion in nano/CMOS (CMOL) FPGA circuits and route them successfully where CMOLCAD tool cannot route
them without congestion. CMOL FPGA architecture, with T basic cells and a latch cell per tile, uses K basic cells (which is
predefined by user), a latch cell for logic implementation and (T-K) cells for routing issue. When the circuit encountered
congestion, CMOLCAD tool decreases K to route the circuits. In this proposed method, we keep and rank the placement
solutions in some of the last iterations of placement algorithm, according to the cost then use them for routing the circuits
with more options. If the routing on the highest priority placement solution has failed, this solution will be removed from the
ranking and another placement solution will be used according to the ranking. The results of applying the proposed method
on some of benchmark circuits indicate that we can route the failed routing nano/CMOS circuits without change the structure.
Silicon technology continues to advance towards the end of
Moores Law, predicted with the end of CMOS scaling only 1015
years away. The theorical and experimental [1, 2] results indicate that
the plausible alternative for current technology is hybrid
semiconductor/ nanodevices circuits. This structure uses the
functionality of programmable diodes (latching-switches) in crossbar
structure (Fig. 1.a) beside the silicon chip. The functionality of such
devices is illustrated in Fig.1.1b. CMOS Molecular (CMOL) [3]
architecture basically called hybrid nanowire/ molecular/
semiconductor circuit which incorporates the nanodevices and
nanowire crossbar into the CMOS IC implementation. CMOL
technology uses the advantages of nano and CMOS technology
together.
(a)
proposed method routes the circuit without congestion by predefined
K or we test all of the kept solutions. In this procedure the cell
connectivity domain (A) is constant. In fact we use routing driven
placement for nano FPGA circuits. For testing the feasibility and
efficiency of the proposed method we have selected 10 circuits
(MCNC benchmark and some of other circuits) that CMOLCAD tool
cannot route them without congestion by predefined values of A and
K. Each circuit has been implemented by original CMOLCAD and
our proposed method. In original CMOLCAD, the circuits could not
be routed successfully on final placement platform but the proposed
method can route these failed routing circuits successfully. The
results show that our method results in only 1.5% and 1% increase in
area and timing cost respectively for total cost of ten circuits.
Total analysis shows that the additional CPU time for running our
method for ten circuits is 26.5 seconds while total time for
CMOLCAD is 313 seconds. This means only 8.5% increase in CPU
time for running our method.
In this paper we first review the nano/CMOS hybrid circuits
(CMOL) and then we discuss about their design automation and
congestion. Finally we explain our method and the results.
In summary the proposed method by a recursive process routes the
nano/CMOS circuits which had faced congestion in CMOLCAD. It
can be seen that by paying negligible additional costs, we route the
failed routing circuits. This method can be added to CMOLCAD and
other nano circuit CADs for removing congestion and route the
circuits successfully with higher probability.
(b)
Figure 1: (a) Nanowire/nanodevice crossbar (b) I-V curve of a twoterminal
crosspoint nanodevice-programmable diode.
Each CMOL FPGA [4, 5] cell uses a basic inverter cell (I-Cell) and
a latch. CMOL CAD utilizes basic and latch cells in square shaped
tiles. Each tile has a latch cell and T basic cell surrounding the
latch. CMOL FPGA uses K basic cells (predefined by user) and a
latch cell for logic implementation and (T-K) cells for routing (Fig.
2). When the circuit encountered congestion, CMOLCAD tool
decreases K to route the circuit. This is a drawback for CMOLCAD
tool that cannot route the circuit with predefined K. In the proposed
method, we keep and rank the placement solutions in some of the last
iterations of placement algorithm according to the cost then use them
for routing the circuits with more options. If the routing on the
highest priority placement solution has failed, this solution will be
removed from ranking and another placement solution will be used
according to the ranking. This procedure will be continued until the
Figure 2: A fragment of two-cell CMOL FPGA fabric
*Corresponding author: alinaderi1998@gmail.com
[1] A. DeHon and K.K. Likharev, in Proc. ICCAD (2005 ).
[2] P .J. Kuekes, G.S. Snider, and R.S. Williams, Sci. American 293
(2005).
[3] D.B. Strukov and K.K. Likharev, in Proc. FPGA, (2006)
[4] D.B. Strukov and K. K. Likharev, Nanotechnology, (2005).
[5] D.B. Strukov, Ph.D. Dissertation, (2006)
6th Nanoscience and Nanotechnology Conference, zmir, 2010 690