GP-B Post-Flight Analysis—Final Report - Gravity Probe B - Stanford ...

11.3.3 Temperature History and Detector High LevelsThe small detector signals must have a large gain applied to match them to the input range of the A/D converter.There also needs to be a means to adjust the DC level of the signal within that range. The sensitivity of theadjustment changes with a different amount of net gain, and there is a small temperature drift of this offset asthe temperature of the warm electronics changes. All of these features were considered in the system design, andseveral operational consequences and results will be discussed. The normal detector signal is reset to an initialcondition, and then as photocurrent integrates on the capacitor, a negative going voltage ramp is produced. Theslope of this waveform contains the information of interest, but it is also desired to know the region of the A/Dconverter range used.The detector signals are digitized in the forward SRE using an A/D converter scaled to accept signals in a 20 Vrange centered about 0 V. Each detector signal is sampled at a rate of 2200 samples per second, to provide 220samples during the tenth second signal interval. The TRE provides a set of selectable gains by which the signaloutput of the CLL preamplifier is increased to provide a better utilization of the range. The Science Slopealgorithm calculates the slope of the detector ramp, but also reports three other signals of interest: detector high,detector mean, and detector low. The detector high signal provides the maximum value of detector sample 14over a 2 second interval (20 consecutive signal integrations). The detector high signal indicates where thebeginning of the ramp will occur, and is usually maintained near 0 V.Timing of the TRE and SRE signals is synchronized using a 10 pps signal called the ATC strobe. The reset of theCLL begins upon the receipt of the ATC strobe and takes a total of approximately 3.5 ms of the 100 ms interval.The charge locked loop is a reset integrator that uses a distributed operational amplifier. A portion of theamplifier is located adjacent to the cold detectors, and the remainder of the amplifier is located in the warmelectronics. There is a solid state switch in the warm area prior to the final stage of the amplifier that is activatedduring the reset interval Figure 11-2 shows the simplified schematic of the detector, feedback capacitor, andswitch states during the signal integration period of operation.Figure 11-2. CLL switch states during normal operationDuring the reset interval, the feedback capacitor is charged to a uniform voltage by switching its terminals totwo low impedance voltages, both of which are adjustable over a small voltage range by changing the eight bitcommand value to the DACs which control the voltages. The detector, feedback capacitor, amplifier input nodeis switched using a reset JFET to a voltage source adjustable approximately ±20 mV from the -4 V amplifierreference node. This DAC is called the offset DAC. See Figure 11-3 for switch states.Gravity Probe B — Post Flight Analysis • Final Report March 2007 313