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GP-B Post-Flight Analysis—Final Report - Gravity Probe B - Stanford ...

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Figure 11-3. CLL switch states during the reset interval.The input of the final amplifier in the charge locked loop is switched during the reset interval to another DACthat provides CLL output voltages between zero and -3.92 V with 256 steps of resolution. This DAC is called theclamp DAC because it clamps the capacitor to a fixed voltage during the reset operation.An adjustment procedure is used to optimize the settings of the two DACs to assure that the preamplifier isreasonably well balanced, and that the DC level of the amplified output is appropriate for the A/D converter.Figure 11-4. CLL switches locked for offset adjustmentIn practice, the offset DAC is adjusted with the reset JFET in an ON state as shown in Figure 11-4. Then theoffset DAC is adjusted to provide the smallest positive voltage output within its resolution. The normal resetclocking is then re-enabled and the clamp DAC is adjusted to provide an operating point within a selectablerange of the A/D converter. Once the adjustments are completed the same command values for the two DACsare used for long periods of time.The cold preamplifiers are each biased using current sources in the warm electronics. As the warm electronicstemperature changes, the 100 μA current sources vary approximately 0.159 μA/°C, so over the ±10 °C operatingrange, the current would change by ±1.6%. While this sensitivity has little effect on the pointing signals derivedfrom the telescope, it causes a minor operational requirement to readjust the clamp command a few timesduring the mission lifetime. The operational results of these adjustments are shown in the figure below.314 March 2007 Chapter 11 — Telescope Readout Subsystem (TRE) Analysis

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