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Appendix D. Site Reports—Japan 251<br />

50Å Ta<br />

300Å CrMnPt<br />

30Å Co<br />

25Å Cu<br />

10Å Co<br />

50Å NiFe<br />

50Å Ta<br />

Figure D.2. Spin valve structure.<br />

1G<br />

1M<br />

DRAM<br />

stills<br />

multimedia<br />

motion picture<br />

storage<br />

1M<br />

1G<br />

1T<br />

Figure D.3. Need for storage capacity, in bytes (Hitachi).<br />

CoCrTa<br />

silicon<br />

Ti<br />

controls structure of magnetic layer<br />

amorphous CrTi<br />

Figure D.4. Perpendicular recording using CoCrTa (Hitachi).<br />

Dr. K. Yano discussed single-electron transistor (SET) memory schemes<br />

(Fig. D.5) where quantum dots would form the gate of the device. He<br />

described a memory cell (0.8 µm x 0.5 µm) comprising the SETs, using a 2.5<br />

V signal to carry out the ‘reading’ of the information bit, 10 V to erase a bit,<br />

<strong>and</strong> 15 V to write a bit. Although 10 7 write <strong>and</strong> erase cycles have been<br />

demonstrated, the operation of this memory cell is still rather slow (on the<br />

order of microseconds). Dr. Yano suggested that SET technology might be<br />

more easily demonstrated in memory devices, rather than in logic devices.

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