PPKE ITK PhD and MPhil Thesis Classes

More documents

Recommendations

Info

82 3. INVESTIGATING THE PRECISION OF PDE SOLVER ARCHITECTURES ON FPGAS 1E-02 1E-03 Error 1E-04 1E-05 1E+02 1E+03 Resolution 1E+04 1E+05 26bit 27bit 28bit 29bit 30bit 31bit 32bit 33bit 34bit Figure 3.8: Error of the 1st order scheme in different precisions and step sizes using fixed-point numbers
3.5 Results 83 arithmetic unit requires only 774 slices from the FPGA, the 40 bit floating-point (which has only 29 bit mantissa) uses 11718 slices. 1.00E-02 1.00E-03 Error 1.00E-04 1.00E-05 1.00E+02 1.00E+03 Resolution 1.00E+04 1.00E+05 29bit fixed 1st order 40bit floating 1st order 40bit floating 2nd order 33bit fixed 1st order Figure 3.9: Comparison of the different type of numbers and the different discretization The goal is to find the finest grid resolution for a given precision where the roundoff and truncation errors are in the same range. This can be easily determined by examining Figure 3.9, where the optimal grid size is located at the minimum point of the error function. The second goal is to find the optimal precision for a given grid resolution. Starting from a low precision simulation and increasing the precision by one bit, the error is halved in each step when the roundoff error is larger than the truncation error. The precision should be increased until the error term can not be decreasing any more. In this point the error of the solution will be dominated by the truncation error and the effect of roundoff error will be negligible.
Page 1:
An Optimal Mapping of Numerical Sim
Page 5 and 6:
Acknowledgements It is not so hard
Page 7 and 8:
Contents 1 Introduction 1 1.1 Cellu
Page 9:
CONTENTS iii 4.3.3 Operating Steps
Page 12 and 13:
vi LIST OF FIGURES 2.4 Performance
Page 15:
List of Tables 2.1 Comparison of di
Page 18 and 19:
xii LIST OF ABBREVIATIONS FPE Falco
Page 21 and 22:
Chapter 1 Introduction Due to the r
Page 23 and 24:
3 can be represented in arbitrary t
Page 25 and 26:
1.1 Cellular Neural/Nonlinear Netwo
Page 27 and 28:
1.2 Cellular Neural/Nonlinear Netwo
Page 29 and 30:
1.3 CNN-UM Implementations 9 the Lo
Page 31 and 32:
1.3 CNN-UM Implementations 11 modif
Page 33 and 34:
1.4 Field Programmable Gate Arrays
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
1.5 IBM Cell Broadband Engine Archi
Page 49 and 50:
1.5 IBM Cell Broadband Engine Archi
Page 51 and 52: 1.5 IBM Cell Broadband Engine Archi
Page 53 and 54: 1.5 IBM Cell Broadband Engine Archi
Page 55 and 56: Chapter 2 Mapping the Numerical Sim
Page 57 and 58: 2.1 Introduction 37 18 Load instruc
Page 59 and 60: 2.1 Introduction 39 Instruction his
Page 61 and 62: 2.1 Introduction 41 2E+07 1E+07 9E+
Page 63 and 64: 2.1 Introduction 43 Main memory 8 t
Page 65 and 66: 2.1 Introduction 45 6 4.5 3 Speedup
Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
Page 69 and 70: 2.2 Ocean model and its implementat
Page 71 and 72: 2.2 Ocean model and its implementat
Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
Page 95 and 96: 3.4 Properties of the Arithmetic Un
Page 97 and 98: 3.4 Properties of the Arithmetic Un
Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 105: 3.6 Conclusion 85 point and the 40
Page 108 and 109: 4. IMPLEMENTING A GLOBAL ANALOGIC P
Page 130 and 131: 110 5. SUMMARY OF NEW SCIENTIFIC RE
Page 141 and 142: References The author’s journal p
Page 143 and 144: 5.2 Application of the results 123
show all

PPKE ITK PhD and MPhil Thesis Classes

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?