PPKE ITK PhD and MPhil Thesis Classes
PPKE ITK PhD and MPhil Thesis Classes
PPKE ITK PhD and MPhil Thesis Classes
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24 1. INTRODUCTION<br />
management, <strong>and</strong> advanced configuration options. Additional platform dependent<br />
features include high-speed serial transceiver blocks for serial connectivity,<br />
PCI Express Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers),<br />
<strong>and</strong> high-performance PowerPC 440 microprocessor embedded blocks.<br />
The XC5VSX95T contains 14,720 slices which builds up from 6-input LUTs<br />
instead of 4-input LUTs as in the previous generations. With the 488 18Kb<br />
SelectRAM blocks it can provide a maximum of 8,784 Kbit RAM. The block<br />
SelectRAM memory resources can be treated as a single or a dual-port RAM,<br />
in this case only 244 blocks are available, in various depth <strong>and</strong> width configurations.<br />
Instead of multipliers it uses 640 DSP48E 18×25 bit slices for accelerating<br />
multiplications <strong>and</strong> multiply-accumulate operations.<br />
The XC5VSX240T contains 37,440 Virtex-5 slices. With the 1,032 18Kb<br />
single-ported SelectRAM blocks, or 516 36Kb dual-ported SelectRAM blocks it<br />
can provide a maximum of 18,576 Kbit RAM in various depth <strong>and</strong> width configurations.<br />
It has also 1056 DSP48E bit slices.<br />
1.4.4.3 The capabilities of the modern Xilinx FPGAs<br />
Built on a 40 nm state-of-the-art copper process technology, Virtex-6 FPGAs are<br />
a programmable alternative to custom ASIC technology.<br />
The look-up tables (LUTs) in Virtex-6 FPGAs can be configured as either<br />
6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit<br />
ROMs) with separate outputs but common addresses or logic inputs. Each LUT<br />
output can optionally be registered in a flip-flop. Four such LUTs <strong>and</strong> their eight<br />
flip-flops as well as multiplexers <strong>and</strong> arithmetic carry logic form a slice, <strong>and</strong> two<br />
slices form a configurable logic block (CLB).<br />
The advanced DSP48E1 slice contains a 25 x 18 multiplier, an adder, <strong>and</strong> an<br />
accumulator. It can optionally pipelined <strong>and</strong> a new optional pre-adder can be<br />
used to assist filtering applications. It also can cascaded due to the dedicated<br />
connections.<br />
It has integrated interface blocks for PCI Express designs compliant to the<br />
PCI Express Base Specification 2.0 with x1, x2, x4, or x8 lane support per block.