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Chapter 3
Investigating the Precision of
PDE Solver Architectures on
FPGAs
Reconfigurable devices seems to be the most versatile devices to implement array
processors. Flexibility of the FPGA devices enable to use different computing
precisions during the solution of PDEs and evaluate different architectures quickly
[30]. Higher computing precision requires wider mantissa which results in larger
implementation area. For that reason it is important to determine the minimal
required computational precision of the algorithm. It is a simple common practice
to use fixed wordlength during the implementation of the datapath on FPGA. The
required silicon area are consumed by a given implementation can be estimated
by the area of the processing units, which is determined mainly by the number
of operations.
In this chapter the optimal precisions with fixed-point and floating-point arithmetic
units on a simple test case is investigated. A single uniform wordlength
was determined in order to have the required accurate solution. There are more
elegant ways to find a more area efficient solutions, like the multiple wordlength
selection problem, but it is proven to be a NP-hard problem [63].
The main motivation of the investigation of the precision was the finite number
of resources. Because different type of problems requires different computational
precision it is necessary to know which problem can be mapped into the FPGA.
In the next section a simple PDE is investigated in order to find a method to
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