PPKE ITK PhD and MPhil Thesis Classes
PPKE ITK PhD and MPhil Thesis Classes
PPKE ITK PhD and MPhil Thesis Classes
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Chapter 2<br />
Mapping the Numerical<br />
Simulations of Partial Differential<br />
Equations<br />
2.1 Introduction<br />
Performance of the general purpose computing systems is usually improved by<br />
increasing the clock frequency <strong>and</strong> adding more processor cores. However, to<br />
achieve very high operating frequency very deep pipeline is required, which cannot<br />
be utilized in every clock cycle due to data <strong>and</strong> control dependencies. If an array<br />
of processor cores is used, the memory system should h<strong>and</strong>le several concurrent<br />
memory accesses, which requires large cache memory <strong>and</strong> complex control logic.<br />
In addition, applications rarely occupy fully all of the available integer <strong>and</strong> floating<br />
point execution units.<br />
Array processing to increase the computing power by using parallel computation<br />
can be a good c<strong>and</strong>idate to solve architectural problems (distribution of<br />
control signals on a chip). Huge computing power is a requirement if we want to<br />
solve complex tasks <strong>and</strong> optimize to dissipated power <strong>and</strong> area at the same time.<br />
In this work the IBM Cell heterogeneous array processor architecture (mainly<br />
because its development system is open source), <strong>and</strong> an FPGA based implementations<br />
is investigated. It is exploited here in solving complex, time consuming<br />
problems.<br />
The main motivation of the Chapter is to find a method for implementing<br />
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