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2.3 Computational Fluid Flow Simulation on Body Fitted Mesh Geometry
with IBM Cell Broadband Engine and FPGA Architecture 61
LOAD
COMPUTE
TEMP
RESULT
STORE
Figure 2.13: Local store buffers
To utilize the power of the Cell architecture computation work should be
distributed between the SPEs. In spite of the large memory bandwidth of the
architecture, the memory bus can be easily saturated. Therefore, an appropriate
arrangement of data between SPEs can greatly improve computing performance.
One possible solution is to distribute grid data between the SPEs. In this case
each SPE work on a narrow horizontal slice of the grid, similarly to the first row
of SPEs in Figure 2.14.
Though the above data arrangement is well suited for the architecture of array
processors and simplifies the inter-processor communication, the eight SPEs
access the main memory in parallel, which might require very high memory bandwidth.
If few instructions are executed on large data sets, the memory system is
saturated resulting in low performance. One possible solution for this problem
is to form a pipeline using the SPEs to compute several iterations in parallel as
shown in Figure 2.14. In this case continuous data flow and synchronization are
required between the neighboring SPEs but this communication pattern is well
suited for the ring structure of the EIB.
The static timing analysis of the optimized CFD solver kernel showed that
a grid point can be updated in approximately 250 clock cycles. Each update
requires moving 64byte data (4x4byte conservative state value, 4x4byte updated
state value, 8x4byte constant value) between the main memory and the local
store of the SPE. The Cell processor runs on 3.2GHz clock frequency, therefore,
in an ideal case the expected performance of the computation kernel using one