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4. IMPLEMENTING A GLOBAL ANALOGIC PROGRAMMING UNIT 96 FOR EMULATED DIGITAL CNN PROCESSORS ON FPGA additional Vector processor units. In this structure - somewhat similar to mixedsignal processors - the duality (mentioned in [68], in the context of analog and logical computing) is expressed in the way timing and control signals are generated for all components by Controller block. The MicroBlaze core is connected across an IPIF interface to the OPB bus, which makes it possible to supply more Falcon processors and Vector processor elements in an array without any significant modifications, and perform operations simultaneously. The entire computation can be started by a single writing operation of a register element. According to the given analog or logical/arithmetical operation, the Command register stores the instructions for Falcon and Vector processors. The Status register shows the current state of the CNN-array. The IterLeft denotes the actual number of the iteration, while the IterCount denotes the maximal number of iterations in the picture, which can be adjusted at the beginning of the computation. The AddrIn and AddrOut counters have to store the start addresses of the ConstBRAM and StateBRAM memories. Each bit-width (e.g., state-, constant-, template-widths) of the entire structure are configurable, thus can be adjusted to the corresponding bit-widths of the Falcon architecture for a specific application. Moreover, owing to the modular structure of the proposed GAPU if the development of a new analogical operation is required, the Command register can be easily extended with a given instruction set of the new function. In order to utilize the high computing power of the modern FPGAs several modification need to perform on the GAPU architecture. The dedicated arithmetic units of the new generation FPGAs becomes faster, while the embedded microprocessors and the used bus systems evolves slower. The implemented Falcon PEs can work much faster than the MicroBlaze processor and its buses. I developed a new architecture in order to work the FPE, the embedded microprocessor, the controller circuit and the memory in different clock speed. This involves the modification of the StateBRAM memories. In spite of using a dualported BRAM, we need to use several single-ported ones. A few to serve the FPEs with datas and one for the MicroBlaze. In this case the relative slow MicroBlaze can monitor the state memories too, while the fast FPE can work continuously. With an additional FIFO element the StateBRAM memory can be reached from
4.3 Implementation 97 outside the GAPU architecture. The new architecture makes it possible for the MicroBlaze, for the control units and for the FPEs to reach the state memories from the outer memory at the same time. 4.3.3 Operating Steps In practice the GAPU works as follows: 1. If we want to compute with an analog operation on an arbitrary sized picture, first a given template should be loaded into the Template BRAM memory. The maximal number of iterations can be set in the IterCount register, and in the Command register the analog operation should be given. The selected template is stored in Template BRAM. 2. The template is loaded from the Template BRAM into the Template memory unit of the Falcon processor. 3. In the next step the AddrIn and AddrOut pixel counters should be initialized along with the iteration counter storing the current step of iteration (IterLeft). The IterLeft gets the value of the IterCount register. 4. When a start (compute) signal is asserted, the GAPU sets the flag of the Command register and Status register to ’1’. Depending on the content of the Command register, it will enable the Falcon processor to work and obtain data from ConstBRAM and StateBRAM memories. During processing the analog operation the Status register shows the operating status of the Falcon processor continuously. 5. If the signal AddrIn En (a valid data is on the input of the processor) is ’true’, the the AddrIn counter is incrementing with the processing of the datas. This counter helps us to monitor the processed datas. If the counter reaches the edge of the picture (the last pixel), its content is deleted. 6. If the Falcon processor has the first results, it sets the DataValidOut signal to ’true’. The way to write the memory is similar to reading the memory. The AddrOut register counts the number of computed pixels, and its content is reseted after the last computed pixel.
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
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CONTENTS iii 4.3.3 Operating Steps
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vi LIST OF FIGURES 2.4 Performance
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List of Tables 2.1 Comparison of di
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xii LIST OF ABBREVIATIONS FPE Falco
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Chapter 1 Introduction Due to the r
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3 can be represented in arbitrary t
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1.1 Cellular Neural/Nonlinear Netwo
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1.2 Cellular Neural/Nonlinear Netwo
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1.3 CNN-UM Implementations 9 the Lo
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1.3 CNN-UM Implementations 11 modif
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1.4 Field Programmable Gate Arrays
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1.5 IBM Cell Broadband Engine Archi
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Chapter 2 Mapping the Numerical Sim
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2.1 Introduction 37 18 Load instruc
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2.1 Introduction 39 Instruction his
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2.1 Introduction 41 2E+07 1E+07 9E+
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2.1 Introduction 43 Main memory 8 t
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Page 73 and 74: 2.3 Computational Fluid Flow Simula
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Page 91 and 92: 3.2 Numerical Solutions of the PDEs
Page 93 and 94: 3.3 Testing Methodology 73 In fixed
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Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
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Page 130 and 131: 110 5. SUMMARY OF NEW SCIENTIFIC RE
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Page 143 and 144: 5.2 Application of the results 123
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PPKE ITK PhD and MPhil Thesis Classes

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