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4.2 Computational background and the optimized Falcon architecture 89
with the sequence of analogic instructions (the program) onto the FPGA, through
merely asserting a ’start’ signal. All the above may be done either without a host
PC, thus our architecture is capable of achieving stand-alone operation, which is
desirable in many industrial contexts. The complex analogic algorithms require
classical program organization elements, i.e., sequential-, iterative- and conditional
execution of instructions. Consequently, the embedded GAPU must be
supplied to the Falcon architecture to extend it to a fully functional CNN-UM
implementation on a reconfigurable FPGA.
4.2 Computational background and the optimized
Falcon architecture
The Falcon architecture implemented on reconfigurable FPGA iterates the forward-
Euler discretized CNN equation by using FSR (Full-Signal Range) model, which
is derived from the original Chua-Yang model [68]. The equations for the Euler
method are as follows:
x m,ij (n + 1) = x m,ij (n) +
g m,ij =
p∑
∑
n=1 kl∈S r(ij)
p∑
∑
n=1 kl∈S r(ij)
A ′ mn,ij,kl · x n,kl (n) + g m,ij (4.1)
B ′ mn,ij,kl · u n,kl (n) + h · z m,ij , (4.2)
where the number of layers is denoted by p, the state of the cell is equal to its
output and limited in the [-1, +1] range. It contains processing elements in a
square grid, and the time-step value h is inserted into the A’ and B’ template
matrices. Moreover, supposing that input is constant or changing slowly, g ij can
be treated as constant and should be calculated only once at the beginning of the
computation.
This multi-layer extension of the elaborated Falcon architecture based on
FPGA [45] can be used for emulating a fully connected multi-layer CNN structure:
both the number of layers and the computing accuracy are configurable.
The main blocks of the Falcon architecture are extended with a low-level Control
unit, which is optimized for GAPU extension, and they are shown in Figure 4.1.