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72 3. INVESTIGATING THE PRECISION OF PDE SOLVER ARCHITECTURES ON FPGAS 3.2.2 The Second-order Limited Scheme The overall accuracy of the scheme can be raised to second-order if the spatial and the temporal derivatives are calculated by a second-order approximation. One way to satisfy the latter requirement is to perform a piecewise linear extrapolation of the primitive variables P L and P R at the two sides of the interface in (3.5). This procedure requires the introduction of additional cells with respect to the interface, i.e. cell LL (left to cell L) and cell RR (right to cell R). With these labels the reconstructed primitive variables are with P L = P L + g L (δP L , δP C ) 2 , P R = P R − g R (δP C , δP R ) , (3.8) 2 δP L = P L − P LL , δP C = P R − P L , δP R = P RR − P R (3.9) while g L and g R are the limiter functions. The previous scheme yields acceptable second-order time-accurate approximation of the solution, only if the variations in the flow field are smooth. In case of discontinuous initial conditions this simple second order approximation can not be used, because the method can be unstable. In order to capture these discontinuities without spurious oscillations, in (3.8) we apply the minmod limiter function, also: ⎧ ⎪⎨ g L (δP L , δP C ) = ⎪⎩ δP L if |δP L | < |δP C | and δP L δP C > 0 δP C if |δP C | < |δP L | and δP L δP C > 0 0 if δP L δP C ≤ 0 The function g R (δP C , δP R ) can be defined analogously. (3.10) 3.3 Testing Methodology The goal of the experiment was to assign an adequate step size and an optimal precision for the problem, which is described by equation (3.1). During the solution different fixed-point and floating point numbers are used. The methodology of the experiment is the investigation of different precision on different grid resolution.
3.3 Testing Methodology 73 In fixed-point case, the precision means the length of the whole number, where 2 bits represents the integer part and the rest is for the fraction, because the numbers are between 0 and 1. In the floating point the exponent length is constant 11 bit wide and the rest is the mantissa, which will be varied during the examination. Current computing architectures are supporting 32 bit floating point or 64 bit double precision numbers for computations. Fixed-point computations can be carried out by using 32 or 64 bit integers. The precision of the fixed- and floating point numbers on FPGA can be defined in much smaller steps. For the computer simulation of the algorithm we used the Mentor Graphics Algorithmic C Datatypes [64], which is a class-based C++ library that provides arbitrary-length fixed-point data types. For different types of floating-point numbers the GNU MPFR library [65] can be used. Despite of the fact, the MPFR contains low-level routines, the first floating-point computations, which we planned to make, took a very long time. Therefore an efficient arithmetic unit were created on FPGA to overcome the slow speed of the arbitrary precision floating-point computations, where the floating point operators from Xilinx CoreGenerator Library [37] are used. The initial condition is a sinus wave and periodic boundary condition is used. The initial conditions was tested because of the simplicity of the sinus function with different precisions, where the result function should match the initial condition after one period. The resolution of the grid is from 100 to 100000 point, the speed of advection is 12/13 and ∆T is 16/17 times the optimal ∆T , which can be computed by the CFL condition. These parameters are selected to meet some critical property, namely it shall not be represented in finite length binary number, on the other hand the number of time steps to compute one period shall be an integer to overcome phase errors. The result was simply compared to the initial condition. The error of the solution is measured by the L ∞ (infinity) norm defined by the following equation: |x| ∞ = max i |x i | (3.11) The method to find a minimal bit width of the arithmetic unit is heuristic. Investigation of different precision operating units are done empirically. With the increase of the bit width a more accurate result can be achieved as can be seen
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An Optimal Mapping of Numerical Sim
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Acknowledgements It is not so hard
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Contents 1 Introduction 1 1.1 Cellu
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CONTENTS iii 4.3.3 Operating Steps
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vi LIST OF FIGURES 2.4 Performance
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List of Tables 2.1 Comparison of di
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xii LIST OF ABBREVIATIONS FPE Falco
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Chapter 1 Introduction Due to the r
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3 can be represented in arbitrary t
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1.1 Cellular Neural/Nonlinear Netwo
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1.2 Cellular Neural/Nonlinear Netwo
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1.3 CNN-UM Implementations 9 the Lo
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1.3 CNN-UM Implementations 11 modif
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1.4 Field Programmable Gate Arrays
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Page 41 and 42: 1.4 Field Programmable Gate Arrays
Page 47 and 48: 1.5 IBM Cell Broadband Engine Archi
Page 55 and 56: Chapter 2 Mapping the Numerical Sim
Page 57 and 58: 2.1 Introduction 37 18 Load instruc
Page 59 and 60: 2.1 Introduction 39 Instruction his
Page 61 and 62: 2.1 Introduction 41 2E+07 1E+07 9E+
Page 63 and 64: 2.1 Introduction 43 Main memory 8 t
Page 65 and 66: 2.1 Introduction 45 6 4.5 3 Speedup
Page 67 and 68: 2.1 Introduction 47 2.50E+07 1.88E+
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Page 73 and 74: 2.3 Computational Fluid Flow Simula
Page 89 and 90: Chapter 3 Investigating the Precisi
Page 91: 3.2 Numerical Solutions of the PDEs
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Page 99 and 100: 3.5 Results 79 in the L2 cache of t
Page 101 and 102: 3.5 Results 81 1E-02 1E-03 Error 1E
Page 103 and 104: 3.5 Results 83 arithmetic unit requ
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Page 141 and 142: References The author’s journal p
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5.2 Application of the results 123
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