PPKE ITK PhD and MPhil Thesis Classes

List of Figures
1.1 Location of the CNN cells on a 2D grid, where the gray cells are
the direct neighbors of the black cell . . . . . . . . . . . . . . . . 4
1.2 The output sigmoid function . . . . . . . . . . . . . . . . . . . . . 5
1.3 Zero- (a) and first-order (b) nonlinearity . . . . . . . . . . . . . . 7
1.4 The architecture of the CNN Universal Machine, the extended
CNN nucleus and the functional blocks of the GAPU . . . . . . . 8
1.5 General architecture of the programmable logic block . . . . . . . 13
1.6 Programmable I/O architecture . . . . . . . . . . . . . . . . . . . 15
1.7 Basic programmable switches . . . . . . . . . . . . . . . . . . . . 16
1.8 Symmetrical wiring . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.9 Cellular wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.10 Row-based wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.11 IBM PowerPC405 processor integration on Xilinx FPGA . . . . . 21
1.12 Block diagram of the Cell processor . . . . . . . . . . . . . . . . . 27
1.13 Block diagram of the functional units of the PowerPC Processor
Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.14 Block diagram of the Synergistic Processor Element . . . . . . . . 30
1.15 IBM Blade Center QS20 architecture . . . . . . . . . . . . . . . . 33
2.1 Generation of the left neighborhood . . . . . . . . . . . . . . . . . 38
2.2 Rearrangement of the state values . . . . . . . . . . . . . . . . . . 38
2.3 Results of the loop unrolling . . . . . . . . . . . . . . . . . . . . . 39
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